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c000000000076420 T __flush_hash_table_range c0000000000766a0 T flush_tlb_pmd_range c0000000000768a0 t native_hpte_find c000000000076990 t native_hpte_remove c000000000076ab0 t native_hpte_insert c000000000076cb0 t native_flush_hash_range c000000000077620 t native_hpte_clear c0000000000778b0 t native_hugepage_invalidate c000000000077fd0 t tlbie c000000000078540 t native_hpte_removebolted c000000000078760 t native_hpte_invalidate c000000000078940 t native_hpte_updatepp c000000000078b60 t native_hpte_updateboltedpp c000000000078dd0 T hash__tlbiel_all c000000000078f60 t __map_kernel_page c000000000079670 T radix__map_kernel_page c000000000079690 T setup_kuep c000000000079720 T setup_kuap c0000000000797c0 T radix__early_init_mmu_secondary c0000000000798a0 T radix__mmu_cleanup_all c000000000079910 T radix__setup_initial_memory_limit c000000000079940 T radix__pmd_hugepage_update c000000000079ab0 T radix__pmdp_collapse_flush c000000000079b20 T radix__pgtable_trans_huge_deposit c000000000079c40 T radix__pgtable_trans_huge_withdraw c000000000079d20 T radix__pmdp_huge_get_and_clear c000000000079e70 T radix__ptep_set_access_flags c000000000079f80 T radix__ptep_modify_prot_commit c00000000007a060 T p4d_free_pud_page c00000000007a070 T pud_set_huge c00000000007a0f0 T pud_clear_huge c00000000007a120 T pud_free_pmd_page c00000000007a270 T pmd_set_huge c00000000007a2f0 T pmd_clear_huge c00000000007a320 T pmd_free_pte_page c00000000007a3b0 t early_alloc_pgtable c00000000007a48c t pte_update.constprop.0 c00000000007a580 T radix__flush_tlb_pwc c00000000007a590 t exit_flush_lazy_tlbs c00000000007a660 t do_tlbiel_kernel c00000000007a800 T radix__flush_tlb_lpid_page c00000000007aaf0 t do_exit_flush_lazy_tlb c00000000007ad40 T radix__flush_pwc_lpid c00000000007ae30 T radix__flush_all_lpid c00000000007b0c0 T radix__local_flush_tlb_mm c00000000007b270 t do_tlbiel_va_range c00000000007b480 t _tlbie_pid c00000000007b970 t do_tlbiel_va c00000000007bbe0 t do_tlbiel_pid c00000000007bfb0 T radix_kvm_prefetch_workaround c00000000007c210 T radix__flush_tlb_kernel_range c00000000007c6f0 t __flush_all_mm c00000000007cdf0 T radix__flush_all_mm c00000000007ce00 T radix__flush_tlb_mm c00000000007d4b0 t __radix__flush_tlb_range c00000000007ed40 T radix__flush_tlb_range c00000000007ed90 T radix__tlbiel_all c00000000007eec0 T radix__local_flush_tlb_page_psize c00000000007efe0 T radix__local_flush_tlb_page c00000000007f040 T radix__flush_tlb_page_psize c00000000007f6d0 T radix__flush_tlb_page c00000000007f730 T radix__flush_all_lpid_guest c00000000007f9c0 T radix__flush_tlb_range_psize c000000000080450 T radix__tlb_flush c000000000081460 T radix__flush_pmd_tlb_range c000000000081480 T radix__flush_tlb_collapsed_pmd c000000000081d80 T radix__flush_tlb_all c000000000081db0 T __rpte_sub_valid c000000000081dd0 T __hash_page_4K c000000000082380 T __hash_page_64K c0000000000828f0 T __hash_page_huge c000000000082ce0 T huge_ptep_modify_prot_start c000000000082e20 T huge_ptep_modify_prot_commit c000000000082e70 T hugetlbpage_init_default c000000000082ed0 T radix__flush_hugetlb_page c000000000083000 T radix__local_flush_hugetlb_page c000000000083130 T radix__flush_hugetlb_tlb_range c000000000083270 T radix__hugetlb_get_unmapped_area c000000000083540 T radix__huge_ptep_modify_prot_commit c000000000083630 T __hash_page_thp c000000000083bb0 t subpage_walk_pmd_entry c000000000083d00 t hpte_flush_range c000000000084070 T __se_sys_subpage_prot c000000000084070 T sys_subpage_prot c000000000084700 T subpage_prot_free c000000000084840 T mm_iommu_preregistered c000000000084860 T mm_iommu_lookup c0000000000848c0 T mm_iommu_ua_to_hpa c000000000084940 T mm_iommu_is_devmem c0000000000849c0 T mm_iommu_mapped_inc c000000000084a10 T mm_iommu_mapped_dec c000000000084a50 T mm_iommu_get c000000000084b40 T mm_iommu_put c000000000084cb0 t mm_iommu_do_alloc c000000000085260 T mm_iommu_new c000000000085280 T mm_iommu_newdev c000000000085290 t mm_iommu_free c000000000085410 T mm_iommu_lookup_rm c000000000085420 T mm_iommu_ua_to_hpa_rm c000000000085500 T mm_iommu_ua_mark_dirty_rm c0000000000855b0 T mm_iommu_init c0000000000855c0 t pkey_initialize c000000000085820 t is_pkey_enabled c000000000085860 t pkey_access_permitted c000000000085970 T pkey_mm_init c0000000000859a0 T __arch_set_user_pkey_access c000000000085aa0 T thread_pkey_regs_save c000000000085af0 T thread_pkey_regs_restore c000000000085b50 T thread_pkey_regs_init c000000000085bb0 T __execute_only_pkey c000000000085bc0 T __arch_override_mprotect_pkey c000000000085c60 T arch_pte_access_permitted c000000000085ca0 T arch_vma_access_permitted c000000000085d30 T arch_dup_pkeys c000000000085d60 t map_cpu_to_node c000000000085e30 t ppc_numa_cpu_dead c000000000085f40 T __node_distance c000000000085ff0 t initialize_distance_lookup_table.part.0 c000000000086080 t of_node_to_nid_single c000000000086160 T of_node_to_nid c000000000086220 t numa_setup_cpu c0000000000863a0 t ppc_numa_cpu_prepare c0000000000864b0 t of_drconf_to_nid_single.isra.0 c0000000000866a0 T cpu_distance c000000000086720 T hot_add_scn_to_nid c000000000086ae0 T memory_hotplug_max c000000000086ba8 t node_set_online c000000000086c30 T get_slice_psize c000000000086c90 t slice_range_to_mask c000000000086db0 t slice_check_range_fits.isra.0 c000000000086f00 t slice_scan_available c000000000086fb0 t slice_flush_segments c000000000087010 t slice_area_is_free.part.0 c0000000000870d0 t slice_find_area_bottomup.isra.0 c000000000087260 t slice_find_area c000000000087550 t slice_convert c000000000087840 T slice_get_unmapped_area c000000000088120 T arch_get_unmapped_area c000000000088150 T arch_get_unmapped_area_topdown c000000000088180 T slice_init_new_context_exec c000000000088340 T slice_setup_new_exec c0000000000883a0 T slice_set_range_psize c000000000088430 T slice_is_hugepage_only_range c000000000088560 t mmu_psize_to_shift.part.0 c000000000088570 T huge_pte_offset c0000000000885b0 T huge_pte_alloc c000000000088bf0 T hugetlb_free_pgd_range c0000000000892f0 T follow_huge_pd c000000000089580 T hugetlb_get_unmapped_area c000000000089660 T vma_mmu_pagesize c0000000000896d0 T flush_dcache_icache_hugepage c0000000000897a0 T copro_handle_mm_fault c000000000089950 T copro_flush_all_slbs c000000000089980 T copro_calculate_slb c000000000089e60 T zalloc_maybe_bootmem c000000000089f00 T is_conditional_branch c000000000089f50 T raw_patch_instruction c000000000089f80 T patch_instruction c000000000089fe0 T patch_branch c00000000008a030 T is_offset_in_branch_range c00000000008a070 T create_branch c00000000008a0c0 T create_cond_branch c00000000008a110 T instr_is_relative_branch c00000000008a140 T instr_is_relative_link_branch c00000000008a180 T branch_target c00000000008a1e0 T instr_is_branch_to_addr c00000000008a250 T translate_branch c00000000008a380 t patch_feature_section c00000000008a500 T do_feature_fixups c00000000008a5c0 T do_stf_barrier_fixups c00000000008aa20 T do_rfi_flush_fixups c00000000008ac80 T do_barrier_nospec_fixups_range c00000000008ad60 T do_barrier_nospec_fixups c00000000008add0 T do_lwsync_fixups c00000000008ae60 T arch_wb_cache_pmem c00000000008aed0 T arch_invalidate_pmem c00000000008aee0 T memcpy_flushcache c00000000008af80 T memcpy_page_flushcache c00000000008afc0 T __copy_from_user_flushcache c00000000008b0f0 T strncpy c00000000008b13c T strncmp c00000000008b174 T memchr c00000000008b1b0 T memcmp c00000000008b850 T override_function_with_return c00000000008b8b4 T __copy_tofrom_user_power7 c00000000008c060 T copypage_power7 c00000000008c220 T memcpy_power7 c00000000008ca00 T __csum_partial c00000000008cb84 T csum_partial_copy_generic c00000000008cdb0 T csum_ipv6_magic c00000000008ce00 T csum_and_copy_to_user c00000000008cfb0 T csum_and_copy_from_user c00000000008d1d0 T __arch_clear_user c00000000008d340 T emulate_update_regs c00000000008d5f0 T emulate_vsx_load c00000000008d9b0 T emulate_vsx_store c00000000008dd50 T analyse_instr c000000000092000 T emulate_dcbz c000000000092130 t do_fp_store c000000000092580 t do_fp_load c000000000092a10 t write_mem c000000000092e20 t read_mem c0000000000932e0 T emulate_loadstore c000000000094d40 T emulate_step c000000000095344 T get_fpr c000000000095480 T put_fpr c0000000000955bc T get_vr c0000000000956f8 T put_vr c000000000095834 T get_vsr c000000000095a54 T put_vsr c000000000095c74 T load_vsrn c000000000095ccc T store_vsrn c000000000095d1c T conv_sp_to_dp c000000000095d48 T conv_dp_to_sp c000000000095d74 T ftr_fixup_test1 c000000000095d80 T end_ftr_fixup_test1 c000000000095d80 T ftr_fixup_test1_orig c000000000095d8c T ftr_fixup_test1_expected c000000000095d98 T ftr_fixup_test2 c000000000095da4 T end_ftr_fixup_test2 c000000000095da4 T ftr_fixup_test2_orig c000000000095db0 T ftr_fixup_test2_alt c000000000095db4 T ftr_fixup_test2_expected c000000000095dc0 T ftr_fixup_test3 c000000000095dcc T end_ftr_fixup_test3 c000000000095dcc T ftr_fixup_test3_orig c000000000095dd8 T ftr_fixup_test3_alt c000000000095de0 T ftr_fixup_test4 c000000000095df8 T end_ftr_fixup_test4 c000000000095df8 T ftr_fixup_test4_expected c000000000095e10 T ftr_fixup_test4_orig c000000000095e28 T ftr_fixup_test4_alt c000000000095e30 T ftr_fixup_test5 c000000000095e54 T end_ftr_fixup_test5 c000000000095e54 T ftr_fixup_test5_expected c000000000095e78 T ftr_fixup_test6 c000000000095ea0 T end_ftr_fixup_test6 c000000000095ea0 T ftr_fixup_test6_expected c000000000095ec8 T ftr_fixup_test7 c000000000095ef0 T end_ftr_fixup_test7 c000000000095ef4 T ftr_fixup_test7_expected c000000000095f18 T ftr_fixup_test_FTR_macros c0000000000960c4 T ftr_fixup_test_FTR_macros_expected c000000000096270 T ftr_fixup_test_FW_FTR_macros c00000000009641c T ftr_fixup_test_FW_FTR_macros_expected c0000000000965c8 T lwsync_fixup_test c0000000000965d0 T end_lwsync_fixup_test c0000000000965d0 T lwsync_fixup_test_expected_LWSYNC c0000000000965d8 T lwsync_fixup_test_expected_SYNC c0000000000967a0 T __xor_altivec_2 c000000000096820 T __xor_altivec_3 c0000000000968b0 T __xor_altivec_4 c000000000096960 T __xor_altivec_5 c000000000096a50 T xor_altivec_2 c000000000096ad0 T xor_altivec_3 c000000000096b60 T xor_altivec_4 c000000000096bf0 T xor_altivec_5 c000000000096c8c T copy_page c000000000096e00 T __copy_tofrom_user c000000000096e0c T __copy_tofrom_user_base c0000000000973b0 T __memset16 c0000000000973b4 T __memset32 c0000000000973b8 T __memset64 c0000000000973c8 T memset c0000000000974cc T memmove c0000000000974e0 T backwards_memcpy c000000000097578 T __arch_hweight8 c000000000097584 T __arch_hweight16 c000000000097598 T __arch_hweight32 c0000000000975b4 T __arch_hweight64 c000000000097680 T memcpy c000000000097710 T memcpy_mcsafe c000000000097990 T enter_vmx_usercopy c0000000000979f0 T exit_vmx_usercopy c000000000097a70 T enter_vmx_ops c000000000097ac0 T exit_vmx_ops c000000000097b2c T do_lq c000000000097b48 T do_stq c000000000097b5c T do_lqarx c000000000097b78 T do_stqcx c000000000097ba0 t mpic_mask_ipi c000000000097bb0 t mpic_host_xlate c000000000097d40 T mpic_get_coreint_irq c000000000097d50 t mpic_host_match c000000000097db0 t mpic_init_sys c000000000097e40 t _mpic_write.isra.0.part.0 c000000000097e60 t fsl_mpic_get_version.part.0 c000000000097eb0 t mpic_suspend c000000000098050 t _mpic_write.isra.0 c0000000000980a0 t mpic_resume c0000000000981f0 T mpic_end_irq c000000000098260 t mpic_end_ipi c000000000098270 t _mpic_cpu_write c0000000000982e0 t mpic_unmask_tm c000000000098430 t mpic_mask_tm c000000000098580 t mpic_unmask_ipi c0000000000986a0 T mpic_unmask_irq c000000000098850 T mpic_mask_irq c000000000098a00 T mpic_set_irq_type c000000000098d00 T mpic_set_affinity c000000000098ed0 t _mpic_get_one_irq c000000000099120 t mpic_cascade c0000000000991e0 T mpic_get_irq c000000000099210 T mpic_set_vector c0000000000993c0 T fsl_mpic_primary_get_version c000000000099400 T mpic_irq_set_priority c0000000000997a0 t mpic_host_map c000000000099ac0 T mpic_setup_this_cpu c000000000099d30 T mpic_cpu_get_priority c000000000099db0 T mpic_cpu_set_priority c000000000099e30 T mpic_teardown_this_cpu c00000000009a0f0 T mpic_get_one_irq c00000000009a100 T mpic_get_mcirq c00000000009a130 T mpic_request_ipis c00000000009a210 T smp_mpic_message_pass c00000000009a310 T smp_mpic_setup_cpu c00000000009a320 T mpic_reset_core c00000000009a548 t _mpic_map_mmio.isra.0 c00000000009a598 t kmalloc_array.constprop.0 c00000000009a5d0 T mpic_msi_reserve_hwirq c00000000009a610 T mpic_msi_init_allocator c00000000009a720 t u3msi_teardown_msi_irqs c00000000009a7d0 t mpic_u3msi_unmask_irq c00000000009a820 t mpic_u3msi_mask_irq c00000000009a870 t find_u4_magic_addr c00000000009a920 t find_ht_magic_addr.isra.0 c00000000009aa70 t u3msi_setup_msi_irqs c00000000009acb0 T mpic_u3msi_init c00000000009ad60 T msi_bitmap_alloc_hwirqs c00000000009ae90 T msi_bitmap_free_hwirqs c00000000009af20 T msi_bitmap_reserve_hwirq c00000000009afa0 T msi_bitmap_reserve_dt_hwirqs c00000000009b190 T msi_bitmap_free c00000000009b220 T msi_bitmap_alloc c00000000009b340 t i8259_host_xlate c00000000009b380 t i8259_host_match c00000000009b3e0 t i8259_host_map c00000000009b470 t i8259_set_irq_mask.isra.0 c00000000009b550 t i8259_mask_irq c00000000009b630 t i8259_unmask_irq c00000000009b710 t i8259_mask_and_ack_irq c00000000009ba20 T i8259_irq c00000000009bed0 T i8259_get_host c00000000009bef0 T i8259_init c00000000009c4b0 t xics_host_match c00000000009c570 t xics_ipi_unmask c00000000009c580 t xics_host_xlate c00000000009c5c0 t xics_host_map c00000000009c6e0 t xics_ipi_mask c00000000009c6f0 T xics_update_irq_servers c00000000009c830 T xics_set_cpu_giq c00000000009c8f0 T xics_setup_cpu c00000000009c950 T xics_teardown_cpu c00000000009c9d0 T xics_kexec_teardown_cpu c00000000009ca60 T xics_migrate_irqs_away c00000000009cd30 T xics_get_irq_server c00000000009ce70 T xics_set_irq_type c00000000009cee0 T xics_retrigger c00000000009cf2c T xics_mask_unknown_vec c00000000009cfc0 t icp_native_teardown_cpu c00000000009d000 t icp_native_flush_ipi c00000000009d040 t icp_native_cause_ipi c00000000009d090 T xics_wake_cpu c00000000009d0c0 t icp_native_set_cpu_priority c00000000009d120 T icp_native_eoi c00000000009d1b0 t icp_native_ipi_action c00000000009d230 t icp_native_get_irq c00000000009d3b0 T icp_native_cause_ipi_rm c00000000009d3f0 T icp_native_flush_interrupt c00000000009d510 t icp_hv_ipi_action c00000000009d5c0 t icp_hv_set_cppr c00000000009d630 t icp_hv_get_irq c00000000009d7f0 t icp_hv_set_cpu_priority c00000000009d890 t icp_hv_flush_ipi c00000000009d910 t icp_hv_eoi c00000000009da00 t icp_hv_cause_ipi c00000000009daa0 t icp_hv_teardown_cpu c00000000009db40 T icp_hv_init c00000000009dbc0 t ics_rtas_host_match c00000000009dc00 t ics_rtas_get_server c00000000009dc80 t ics_rtas_map c00000000009dd70 t ics_rtas_set_affinity c00000000009df20 t ics_rtas_unmask_irq c00000000009e050 t ics_rtas_startup c00000000009e0b0 t ics_rtas_mask_real_irq.part.0 c00000000009e190 t ics_rtas_mask_unknown c00000000009e1b0 t ics_rtas_mask_irq c00000000009e1d0 t ics_opal_host_match c00000000009e1e0 t ics_opal_get_server c00000000009e260 t ics_opal_mask_real_irq c00000000009e2e0 t ics_opal_mask_unknown c00000000009e360 t ics_opal_mask_irq c00000000009e380 t ics_opal_map c00000000009e460 t ics_opal_set_affinity c00000000009e600 t ics_opal_unmask_irq c00000000009e6e0 t ics_opal_startup c00000000009e740 t icp_opal_cause_ipi c00000000009e7a0 t icp_opal_teardown_cpu c00000000009e7e0 t icp_opal_ipi_action c00000000009e850 t icp_opal_flush_ipi c00000000009e890 t icp_opal_set_cpu_priority c00000000009e900 t icp_opal_eoi c00000000009e9a0 t icp_opal_get_xirr.part.0 c00000000009ea20 t icp_opal_get_irq c00000000009ebb0 T icp_opal_flush_interrupt c00000000009ecc0 T icp_opal_init c00000000009ed40 T is_xive_irq c00000000009ed60 t xive_ipi_do_nothing c00000000009ed70 t xive_irq_domain_match c00000000009edc0 t xive_setup_cpu c00000000009ee60 t xive_esb_read c00000000009ef30 t xive_get_irqchip_state c00000000009efe0 t xive_cause_ipi c00000000009f040 t xive_irq_set_type c00000000009f140 t xive_dec_target_count c00000000009f1e0 t xive_find_target_in_mask c00000000009f410 t xive_pick_irq_target c00000000009f620 t xive_irq_set_affinity c00000000009f850 t xive_scan_interrupts c00000000009fab0 t xive_get_irq c00000000009fb40 T xive_cleanup_irq_data c00000000009fbf0 t xive_muxed_ipi_action c00000000009fc20 t xive_irq_domain_unmap c00000000009fcf0 t xive_irq_domain_xlate c00000000009fd30 t xive_do_source_set_mask.part.0 c00000000009fd90 t xive_irq_mask c00000000009fe20 t xive_irq_shutdown c00000000009fef0 t xive_do_source_set_mask.constprop.0 c00000000009ff80 t xive_irq_startup c0000000000a0110 t xive_setup_cpu_ipi c0000000000a02b0 t xive_irq_unmask c0000000000a0350 t xive_do_source_eoi c0000000000a0520 t xive_irq_set_vcpu_affinity c0000000000a07a0 t xive_irq_retrigger c0000000000a0810 t xive_irq_eoi c0000000000a08d0 t xive_flush_cpu_queue.isra.0 c0000000000a0a10 t xive_prepare_cpu c0000000000a0ba0 t xive_irq_domain_map c0000000000a0d20 t xive_ipi_eoi c0000000000a0db0 T xmon_xive_do_dump c0000000000a0f30 T xmon_xive_get_irq_config c0000000000a10e0 T xive_smp_setup_cpu c0000000000a1110 T xive_smp_prepare_cpu c0000000000a1170 T xive_smp_disable_cpu c0000000000a1230 T xive_flush_interrupt c0000000000a1250 T xive_teardown_cpu c0000000000a13b0 T xive_shutdown c0000000000a13f0 T xive_queue_page_alloc c0000000000a14d0 T xive_native_default_eq_shift c0000000000a14f0 T xive_native_has_single_escalation c0000000000a1510 T xive_native_populate_irq_data c0000000000a1730 T xive_native_configure_irq c0000000000a17d0 T xive_native_get_queue_info c0000000000a1920 T xive_native_configure_queue c0000000000a1b40 T xive_native_alloc_irq c0000000000a1be0 t xive_native_get_ipi c0000000000a1c90 T xive_native_free_irq c0000000000a1cf0 T xive_native_sync_source c0000000000a1d30 T xive_native_sync_queue c0000000000a1d70 t xive_native_shutdown c0000000000a1da0 t xive_native_eoi c0000000000a1dd0 t xive_native_update_pending c0000000000a1ec0 t xive_native_match c0000000000a1f00 t xive_native_teardown_cpu c0000000000a1fa0 T xive_native_enable_vp c0000000000a2040 T xive_native_disable_vp c0000000000a20c0 t xive_native_setup_cpu c0000000000a2280 T xive_native_get_vp_info c0000000000a2330 t xive_native_setup_queue c0000000000a2400 t xive_native_get_irq_config c0000000000a24a0 T xive_native_alloc_vp_block c0000000000a2610 T xive_native_get_queue_state c0000000000a2700 T xive_native_set_queue_state c0000000000a2780 T xive_native_has_queue_state_support c0000000000a27f0 T xive_native_get_vp_state c0000000000a28a0 t __xive_native_disable_queue.isra.0 c0000000000a2950 T xive_native_disable_queue c0000000000a2960 t xive_native_cleanup_queue c0000000000a2a00 t xive_native_put_ipi c0000000000a2a80 T xive_native_free_vp_block c0000000000a2ae0 t xive_spapr_match c0000000000a2af0 t xive_spapr_put_ipi c0000000000a2c40 t xive_spapr_eoi c0000000000a2c50 t xive_spapr_setup_cpu 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