8( @radxa,rock-5arockchip,rk3588s +7Radxa ROCK 5 Model Acpus+cpu-mapcluster0core0=core1=core2=core3=cluster1core0=core1=cluster2core0=core1= cpu@0Acpuarm,cortex-a55MQpsci_r y 0, @@ 1@ Kcpu@100Acpuarm,cortex-a55MQpsci_r  @@1@ Kcpu@200Acpuarm,cortex-a55MQpsci_r  @@1@ Kcpu@300Acpuarm,cortex-a55MQpsci_r  @@1@ Kcpu@400Acpuarm,cortex-a76MQpsci_r y 0, @@1@Kcpu@500Acpuarm,cortex-a76MQpsci_r  @@1@Kcpu@600Acpuarm,cortex-a76MQpsci_r y 0, @@1@Kcpu@700Acpuarm,cortex-a76MQpsci_r  @@1@K idle-statesSpscicpu-sleeparm,idle-state`qdxK l2-cache-l0cache@K l2-cache-l1cache@Kl2-cache-l2cache@Kl2-cache-l3cache@Kl2-cache-b0cache@Kl2-cache-b1cache@Kl2-cache-b2cache@Kl2-cache-b3cache@Kl3-cachecache0@Kfirmwareopteelinaro,optee-tzXsmcscmi arm,scmi-smcԂ+protocol@14MK protocol@16Mpmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0Xsmcclock-0 fixed-clock )׫splltimerarm,armv8-timerP    %-sec-physphysvirthyp-physhyp-virtclock-1 fixed-clock n6xin24mclock-2 fixed-clock xin32ksram@10f000 mmio-sramM=+sram@0arm,scmi-shmemMKusb@fc800000"rockchip,rk3588-ehcigeneric-ehciMrDIusbSaokayhdefaultv !"#usb@fc840000"rockchip,rk3588-ohcigeneric-ohciMrDIusbSaokayusb@fc880000"rockchip,rk3588-ehcigeneric-ehciMr$D%IusbSaokayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohciMr$D%IusbSaokaysyscon@fd58c000rockchip,rk3588-sys-grfsysconMXKesyscon@fd5b0000rockchip,rk3588-php-grfsysconM[K'syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsysconM[Ksyscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsysconM\@Ksyscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdM]@+usb2-phy@8000rockchip,rk3588-usb2phyMophyapbrphyclk usb480m_phy2aokayKhost-portaokay&Ksyscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdM]@+usb2-phy@c000rockchip,rk3588-usb2phyMp phyapbrphyclk usb480m_phy3aokayK$host-portaokay&K%syscon@fd5f0000rockchip,rk3588-iocsysconM_Ksram@fd600000 mmio-sramM`=`+clock-controller@fd7c0000rockchip,rk3588-cruM|y]q@A.2Fq)׫ׄe/ׄ eZ р 'Ki2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2cM=rts i2cpclkv(hdefault+aokayregulator@42rockchip,rk8602MBvdd_cpu_big0_s0dp,DY)Kregulator-state-memdregulator@43 rockchip,rk8603rockchip,rk8602MCvdd_cpu_big1_s0dp,DY)Kregulator-state-memdserial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartMKrbaudclkapb_pclk}**txrxv+hdefault adisabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMr pwmpclkv,hdefault adisabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMr pwmpclkv-hdefault adisabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM r pwmpclkv.hdefault adisabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0r pwmpclkv/hdefaultaokayKpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfdMpower-controller!rockchip,rk3588-power-controller+aokayKpower-domain@8M+power-domain@9M  r!#" 012+power-domain@10M r!#"3power-domain@11M r!#"4power-domain@12M r5678power-domain@13M +power-domain@14M(r9power-domain@15M r:power-domain@16Mr ;<=+power-domain@17M r >?@power-domain@21Mr ABCDEFGH+power-domain@23MrCAIpower-domain@14M r9power-domain@15Mr:power-domain@22MrJpower-domain@24Mr[Z]KL+power-domain@25M8rZMpower-domain@26M8rQNOpower-domain@27M0rPQRS+power-domain@28M rTUpower-domain@29M(rVWpower-domain@30Mrz{Xpower-domain@31M@rWYZ[\power-domain@33M!rWZ[power-domain@34M"rWZ[power-domain@37M%r2]power-domain@38M&r45power-domain@40M(^i2s@fddc0000rockchip,rk3588-i2s-tdmMrmclk_txmclk_rxhclky}_txStx-m adisabledi2s@fddf0000rockchip,rk3588-i2s-tdmMr445mclk_txmclk_rxhclky1}_txStx-m adisabledi2s@fddfc000rockchip,rk3588-i2s-tdmMr00,mclk_txmclk_rxhclky-}_rxSrx-m adisabledqos@fdf35000rockchip,rk3588-qossysconMP K5qos@fdf35200rockchip,rk3588-qossysconMR K6qos@fdf35400rockchip,rk3588-qossysconMT K7qos@fdf35600rockchip,rk3588-qossysconMV K8qos@fdf36000rockchip,rk3588-qossysconM` KXqos@fdf39000rockchip,rk3588-qossysconM K]qos@fdf3d800rockchip,rk3588-qossysconM K^qos@fdf3e000rockchip,rk3588-qossysconM KZqos@fdf3e200rockchip,rk3588-qossysconM KYqos@fdf3e400rockchip,rk3588-qossysconM K[qos@fdf3e600rockchip,rk3588-qossysconM K\qos@fdf40000rockchip,rk3588-qossysconM KVqos@fdf40200rockchip,rk3588-qossysconM KWqos@fdf40400rockchip,rk3588-qossysconM KPqos@fdf40500rockchip,rk3588-qossysconM KQqos@fdf40600rockchip,rk3588-qossysconM KRqos@fdf40800rockchip,rk3588-qossysconM KSqos@fdf41000rockchip,rk3588-qossysconM KTqos@fdf41100rockchip,rk3588-qossysconM KUqos@fdf60000rockchip,rk3588-qossysconM K;qos@fdf60200rockchip,rk3588-qossysconM K<qos@fdf60400rockchip,rk3588-qossysconM K=qos@fdf61000rockchip,rk3588-qossysconM K>qos@fdf61200rockchip,rk3588-qossysconM K?qos@fdf61400rockchip,rk3588-qossysconM K@qos@fdf62000rockchip,rk3588-qossysconM K9qos@fdf63000rockchip,rk3588-qossysconM0 K:qos@fdf64000rockchip,rk3588-qossysconM@ KIqos@fdf66000rockchip,rk3588-qossysconM` KAqos@fdf66200rockchip,rk3588-qossysconMb KBqos@fdf66400rockchip,rk3588-qossysconMd KCqos@fdf66600rockchip,rk3588-qossysconMf KDqos@fdf66800rockchip,rk3588-qossysconMh KEqos@fdf66a00rockchip,rk3588-qossysconMj KFqos@fdf66c00rockchip,rk3588-qossysconMl KGqos@fdf66e00rockchip,rk3588-qossysconMn KHqos@fdf67000rockchip,rk3588-qossysconMp KJqos@fdf67200rockchip,rk3588-qossysconMr qos@fdf70000rockchip,rk3588-qossysconM K3qos@fdf71000rockchip,rk3588-qossysconM K4qos@fdf72000rockchip,rk3588-qossysconM K0qos@fdf72200rockchip,rk3588-qossysconM" K1qos@fdf72400rockchip,rk3588-qossysconM$ K2qos@fdf80000rockchip,rk3588-qossysconM KMqos@fdf81000rockchip,rk3588-qossysconM KNqos@fdf81200rockchip,rk3588-qossysconM KOqos@fdf82000rockchip,rk3588-qossysconM KKqos@fdf82200rockchip,rk3588-qossysconM" KLpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0rCH>MR)aclk_mstaclk_slvaclk_dbipclkauxpipeApciP-syspmcmsglegacyerr `````->M0a0UDb Ipcie-phyS"T= @ @0M @@_dbiapbconfig). pwrpipe+ adisabledlegacy-interrupt-controlleri K`pcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O0rDI?NSs)aclk_mstaclk_slvaclk_dbipclkauxpipeApciP-syspmcmsglegacyerr `cccc->M@a@UDd Ipcie-phyS"T= @ @0M A@_dbiapbconfig*/ pwrpipe+ adisabledlegacy-interrupt-controlleri Kcethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20aM -macirqeth_wake_irq(r67Y^50stmmacethclk_mac_refpclk_macaclk_macptp_refS!$ stmmacethe~'fghaokayoutputirgmiivjklmnhdefault: >mdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916MhdefaultvoN " 4pKistmmac-axi-config@JZKfrx-queues-configjKgqueue0queue1tx-queues-configKhqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciM!(rb_eTosatapmaliverxoobrefasic+ adisabledsata-port@0M@Dd Isata-phy  sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciM#(rdagVqsatapmaliverxoobrefasic+ adisabledsata-port@0M@Db Isata-phy  mmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcM,@ r  biuciuciu-driveciu-sampleрhdefaultvqrstS(aokay u"-5<JvVwmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcM-@ rbiuciuciu-driveciu-sample hdefaultvxS% adisabledmmc@fe2e0000rockchip,rk3588-dwcmshcM.y-., n6 (r,*+-.corebusaxiblocktimer vyz{|}hdefault(corebusaxiblocktimeraokay-ciwi2s@fe470000rockchip,rk3588-i2s-tdmMGr+/(mclk_txmclk_rxhclky)-}**txrxS&*+ tx-mrx-mhdefaultv~aokayportKendpointi2sKi2s@fe480000rockchip,rk3588-i2s-tdmMHry}umclk_txmclk_rxhclk}**txrx^_ tx-mrx-mhdefault(v adisabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sMIri2s_clki2s_hclky}txrxS&hdefaultv adisabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sMJr%i2s_clki2s_hclky"}txrxS&hdefaultv adisabledinterrupt-controller@fe600000 arm,gic-v3 M`h ia8=+Kmsi-controller@fe640000arm,gic-v3-itsMdKamsi-controller@fe660000arm,gic-v3-itsMfppi-partitionsinterrupt-partition-0 Kinterrupt-partition-1  Kdma-controller@fea10000arm,pl330arm,primecellM@ VWrn apb_pclk-K*dma-controller@fea30000arm,pl330arm,primecellM@ XYro apb_pclk-Ki2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2cMr{ i2cpclk>vhdefault+ adisabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr| i2cpclk?vhdefault+aokayregulator@42rockchip,rk8602MB vdd_npu_s0dp,~DY)regulator-state-memdeeprom@50belling,bl24c16aatmel,24c16MP8i2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr} i2cpclk@vhdefault+aokayi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr~ i2cpclkAvhdefault+ adisabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr i2cpclkBvhdefault+aokaytimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timerM !rTW pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdtMrdc tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiMFrspiclkapb_pclk}**txrxA vhdefault+ adisabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiMGrspiclkapb_pclk}**txrxA vhdefault+ adisabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiMHrspiclkapb_pclk}txrxAvhdefault+aokayy pmic@0rockchip,rk806M uhdefaultvHB@Z)f)r)~)))))))))#dvs1-null-pins/gpio_pwrctrl2 4pin_fun0Kdvs2-null-pins/gpio_pwrctrl2 4pin_fun0Kdvs3-null-pins/gpio_pwrctrl3 4pin_fun0Kregulatorsdcdc-reg1 vdd_gpu_s0dp,~D0=regulator-state-memddcdc-reg2vdd_cpu_lit_s0dp,~D0K regulator-state-memddcdc-reg3 vdd_log_s0 L, qD0regulator-state-memdY qdcdc-reg4 vdd_vdenc_s0dp,~D0regulator-state-memddcdc-reg5 vdd_ddr_s0 L, D0regulator-state-memdY Pdcdc-reg6 vdd2_ddr_s3regulator-state-memudcdc-reg7vdd_2v0_pldo_s3,D0Kregulator-state-memuYdcdc-reg8 vcc_3v3_s32Z,2Zregulator-state-memuY2Zdcdc-reg9 vddq_ddr_s0regulator-state-memddcdc-reg10 vcc_1v8_s3w@,w@regulator-state-memuYw@pldo-reg1 avcc_1v8_s0w@,w@Kregulator-state-memdpldo-reg2 vcc_1v8_s0w@,w@regulator-state-memdYw@pldo-reg3 avdd_1v2_s0O,Oregulator-state-memdpldo-reg4 vcc_3v3_s02Z,2ZD0Kvregulator-state-memdpldo-reg5 vccio_sd_s0w@,2ZD0Kwregulator-state-memdpldo-reg6 pldo6_s3w@,w@regulator-state-memuYw@nldo-reg1 vdd_0v75_s3 q, qregulator-state-memuY qnldo-reg2vdd_ddr_pll_s0 P, Pregulator-state-memdY Pnldo-reg3 avdd_0v75_s0 q, qregulator-state-memdnldo-reg4 vdd_0v85_s0 P, Pregulator-state-memdnldo-reg5 vdd_0v75_s0 q, qregulator-state-memdspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiMIrspiclkapb_pclk}txrxA vhdefault+ adisabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartMLrbaudclkapb_pclk}** txrxvhdefault adisabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartMMrbaudclkapb_pclk}* * txrxvhdefaultaokayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartMNrbaudclkapb_pclk}* * txrxvhdefault adisabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartMOrbaudclkapb_pclk} txrxvhdefault adisabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartMPrbaudclkapb_pclk} txrxvhdefault adisabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartMQrbaudclkapb_pclk} txrxvhdefault adisabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartMRrbaudclkapb_pclk}__txrxvhdefault adisabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartMSrbaudclkapb_pclk}_ _ txrxvhdefault adisabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartMTrbaudclkapb_pclk}_ _ txrxvhdefault adisabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrLK pwmpclkvhdefault adisabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrLK pwmpclkvhdefault adisabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rLK pwmpclkvhdefault adisabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rLK pwmpclkvhdefault adisabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrON pwmpclkvhdefault adisabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrON pwmpclkvhdefault adisabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rON pwmpclkvhdefault adisabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rON pwmpclkvhdefault adisabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrRQ pwmpclkvhdefault adisabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrRQ pwmpclkvhdefault adisabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rRQ pwmpclkvhdefault adisabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rRQ pwmpclkvhdefault adisabledtsadc@fec00000rockchip,rk3588-tsadcMrtsadcapb_pclkyVWtsadc-apbtsadcv hgpiootpout adisabledadc@fec10000rockchip,rk3588-saradcMrsaradcapb_pclkU saradc-apbaokay i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2cMr i2cpclkCvhdefault+ adisabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2cMr i2cpclkDvhdefault+aokayaudio-codec@11everest,es8316Mr1mclky1portendpointKi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr i2cpclkEvhdefault+ adisabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiMJrspiclkapb_pclk}_ _txrxA vhdefault+ adisabledefuse@fecc0000rockchip,rk3588-otpM rotpapb_pclkphyarb otpapbarb+cpu-code@2Mid@7Mcpu-leakage@17Mcpu-leakage@18Mcpu-leakage@19Mlog-leakage@1aMgpu-leakage@1bMcpu-version@1cM npu-leakage@28M(codec-leakage@29M)dma-controller@fed10000arm,pl330arm,primecellM@ Z[rp apb_pclk-K_phy@fee00000rockchip,rk3588-naneng-combphyMrvW refapbpipey<Cphyapb ' + adisabledKdphy@fee20000rockchip,rk3588-naneng-combphyMrxW refapbpipey>Ephyapb ' + adisabledKbsram@ff001000 mmio-sramM=+pinctrlrockchip,rk3588-pinctrl=+Kgpio@fd8a0000rockchip,gpio-bankMrqr A i#Kugpio@fec20000rockchip,gpio-bankMrst A i#gpio@fec30000rockchip,gpio-bankMruv A@ i#gpio@fec40000rockchip,gpio-bankMrwx A` i#Kpgpio@fec50000rockchip,gpio-bankMryz A i#Kpcfg-pull-up MKpcfg-pull-down ZKpcfg-pull-none iKpcfg-pull-none-drv-level-2 i vKpcfg-pull-up-drv-level-1 M vKpcfg-pull-up-drv-level-2 M vKpcfg-pull-none-smt i Kpcfg-output-high Kauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout Kyemmc-bus8 Kzemmc-clk K{emmc-cmd K|emmc-data-strobe K}eth1fspigmac1gmac1-miim Kjgmac1-rx-bus20  Klgmac1-tx-bus20    Kkgmac1-rgmii-clk Kmgmac1-rgmii-bus@ Kngpuhdmii2c0i2c0m2-xfer K(i2c1i2c1m0-xfer  Ki2c2i2c2m0-xfer   Ki2c3i2c3m0-xfer   Ki2c4i2c4m0-xfer   Ki2c5i2c5m2-xfer   Ki2c6i2c6m0-xfer   Ki2c7i2c7m0-xfer   Ki2c8i2c8m0-xfer   Ki2s0i2s0-lrck K~i2s0-mclk Ki2s0-sclk Ki2s0-sdi0 Ki2s0-sdo0 Ki2s1i2s1m0-lrck Ki2s1m0-sclk Ki2s1m0-sdi0 Ki2s1m0-sdi1 Ki2s1m0-sdi2 Ki2s1m0-sdi3 Ki2s1m0-sdo0  Ki2s1m0-sdo1  Ki2s1m0-sdo2  Ki2s1m0-sdo3  Ki2s2i2s2m1-lrck Ki2s2m1-sclk  Ki2s2m1-sdi  Ki2s2m1-sdo  Ki2s3i2s3-lrck Ki2s3-sclk Ki2s3-sdi Ki2s3-sdo Kjtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp Kpmupwm0pwm0m0-pins K,pwm1pwm1m0-pins K-pwm2pwm2m0-pins K.pwm3pwm3m1-pins  K/pwm4pwm4m0-pins  Kpwm5pwm5m0-pins Kpwm6pwm6m0-pins  Kpwm7pwm7m0-pins  Kpwm8pwm8m0-pins  Kpwm9pwm9m0-pins  Kpwm10pwm10m0-pins  Kpwm11pwm11m0-pins  Kpwm12pwm12m0-pins  Kpwm13pwm13m0-pins  Kpwm14pwm14m0-pins  Kpwm15pwm15m0-pins  Krefclksatasata0sata1sata2sdiosdiom1-pins` Kxsdmmcsdmmc-bus4@ Ktsdmmc-clk Kqsdmmc-cmd Krsdmmc-det Ksspdif0spdif1spi0spi0m0-pins0 Kspi0m0-cs0 Kspi0m0-cs1 Kspi1spi1m1-pins0 Kspi1m1-cs0 Kspi1m1-cs1 Kspi2spi2m2-pins0  Kspi2m2-cs0 Kspi3spi3m1-pins0  Kspi3m1-cs0 Kspi3m1-cs1 Kspi4spi4m0-pins0 Kspi4m0-cs0 Kspi4m0-cs1 Ktsadctsadc-shut Kuart0uart0m1-xfer  K+uart1uart1m1-xfer   Kuart2uart2m0-xfer  Kuart3uart3m1-xfer   Kuart4uart4m1-xfer   Kuart5uart5m1-xfer   Kuart6uart6m1-xfer   Kuart7uart7m1-xfer   Kuart8uart8m1-xfer   Kuart9uart9m1-xfer   Kvopbt656gpio-functsadc-gpio-func Kledsio-led Kpowervcc-5v0-en Krtl8211frtl8211f-rst Kousbvcc5v0-host-en  Kwifibtwl-reset Kwl-dis K wl-wake-host K!bt-dis K"bt-wake-host K#aliases /mmc@fe2e0000 /mmc@fe2c0000 /serial@feb50000analog-soundaudio-graph-card rk3588-es8316) MicrophoneMic JackHeadphoneHeadphones. MIC2Mic JackHeadphonesHPOLHeadphonesHPOR chosen serial2:1500000n8leds gpio-ledshdefaultvio-led 4status :p heartbeatpwm-fanpwm-fan _  #P1vcc12v-dcin-regulatorregulator-fixed vcc12v_dcin,Kvcc5v0-host-regulatorregulator-fixed vcc5v0_hostLK@,LK@ ( ; hdefaultvY)K&vcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@,LK@YK)vcc-5v0-regulatorregulator-fixedvcc_5v0LK@,LK@ ( ;hdefaultvY)Kvcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s3,Y)K compatibleinterrupt-parent#address-cells#size-cellsmodelcpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesphysphy-namespower-domainsstatuspinctrl-namespinctrl-0resetsreset-namesclock-names#phy-cellsphy-supplyrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreg-namesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modetx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlydai-formatmclk-fsremote-endpointmbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellspagesizenum-csspi-max-frequencyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplybitsrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highrockchip,pinsmmc0mmc1serial2labelwidgetsroutingdaisstdout-pathcolorlinux,default-triggercooling-levelsfan-supplypwmsenable-active-highgpio