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KZethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20aM -macirqeth_wake_irq(r67Y^50{stmmacethclk_mac_refpclk_macaclk_macptp_refS!h$ ostmmaceth\]^_ adisabledmdiosnps,dwmac-mdio+stmmac-axi-config#3K]rx-queues-configCK^queue0queue1tx-queues-configYK_queue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciM!(rb_eTo{satapmaliverxoobrefasico+aokaysata-port@0M@D[ Isata-phy  sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciM#(rdagVq{satapmaliverxoobrefasico+ adisabledsata-port@0M@DY Isata-phy  mmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcM,@ r  {biuciuciu-driveciu-sample default`abcS(aokay d&emmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcM-@ r{biuciuciu-driveciu-sample defaultfS% adisabledmmc@fe2e0000rockchip,rk3588-dwcmshcM.y-., n6 (r,*+-.{corebusaxiblocktimer ghijkdefault(hocorebusaxiblocktimeraokay39GVi2s@fe470000rockchip,rk3588-i2s-tdmMGr+/({mclk_txmclk_rxhclky)-!!txrxS&h*+ otx-mrx-mpdefault(lmnopqrstu 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vdd2_ddr_s3|regulator-state-memdcdc-reg7vdd_2v0_pldo_s3|20Kregulator-state-memdcdc-reg8 vcc_3v3_s3|2Z2ZKdregulator-state-mem2Zdcdc-reg9 vddq_ddr_s0|regulator-state-memcdcdc-reg10 vcc_1v8_s3|w@w@regulator-state-memw@pldo-reg1 avcc_1v8_s0|w@w@regulator-state-memcpldo-reg2 vcc_1v8_s0|w@w@regulator-state-memcw@pldo-reg3 avdd_1v2_s0|OOregulator-state-memcpldo-reg4 vcc_3v3_s0|2Z2Z20regulator-state-memcpldo-reg5 vccio_sd_s0|w@2Z20Keregulator-state-memcpldo-reg6 pldo6_s3|w@w@regulator-state-memw@nldo-reg1 vdd_0v75_s3| q qregulator-state-mem qnldo-reg2vdd_ddr_pll_s0| P Pregulator-state-memc Pnldo-reg3 avdd_0v75_s0| q qregulator-state-memcnldo-reg4 vdd_0v85_s0| P Pregulator-state-memcnldo-reg5 vdd_0v75_s0| q qregulator-state-memcspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiMIr{spiclkapb_pclktxrx default+ adisabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartMLr{baudclkapb_pclk!! txrxdefault adisabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartMMr{baudclkapb_pclk! ! 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adisabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrON {pwmpclkdefault adisabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrON {pwmpclkdefault adisabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rON {pwmpclkdefault adisabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rON {pwmpclkdefault adisabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrRQ {pwmpclkdefault adisabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrRQ {pwmpclkdefault adisabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rRQ {pwmpclkdefault adisabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rRQ {pwmpclkdefault adisabledtsadc@fec00000rockchip,rk3588-tsadcMr{tsadcapb_pclkyhVWotsadc-apbtsadc & gpiootpout0 adisabledadc@fec10000rockchip,rk3588-saradcMFr{saradcapb_pclkhU osaradc-apb adisabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2cMr {i2cpclkCdefault+aokayrtc@51haoyu,hym8563MQ hym8563defaultXi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2cMr 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adisabledi2s@fddf4000rockchip,rk3588-i2s-tdmM@r99?{mclk_txmclk_rxhclky6VtxShotx-m adisabledi2s@fddf8000rockchip,rk3588-i2s-tdmM߀r++'{mclk_txmclk_rxhclky(VrxShorx-m adisabledi2s@fde00000rockchip,rk3588-i2s-tdmMr&&"{mclk_txmclk_rxhclky#VrxShorx-m adisabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie++0r@E;JOt){aclk_mstaclk_slvaclk_dbipclkauxpipeApciP-syspmcmsglegacyerr5F`YgxD Ipcie-phyS"T= @ @0M @@dbiapbconfigh&+ opwrpipe adisabledlegacy-interrupt-controller5 Kpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie++0rAF<KPu){aclk_mstaclk_slvaclk_dbipclkauxpipeApciP-syspmcmsglegacyerr5F`YgxD Ipcie-phyS"T= @ @@0M @@@dbiapbconfigh', opwrpipe adisabledlegacy-interrupt-controller5 Kpcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie+ /0rBG=LQ){aclk_mstaclk_slvaclk_dbipclkauxpipeApciP-syspmcmsglegacyerr5F`Ygx X D Ipcie-phyS"T= @ @0M @@dbiapbconfigh(- opwrpipe+ adisabledlegacy-interrupt-controller5 Kethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20aM -macirqeth_wake_irq(r67X]40{stmmacethclk_mac_refpclk_macaclk_macptp_refS!h# ostmmaceth\ adisabledmdiosnps,dwmac-mdio+stmmac-axi-config#3Krx-queues-configCKqueue0queue1tx-queues-configYKqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciM"(rc`fUp{satapmaliverxoobrefasico+ adisabledsata-port@0M@D Isata-phy  phy@fee10000rockchip,rk3588-naneng-combphyMrwW {refapbpipeyh=Dophyapbk} adisabledKphy@fee80000rockchip,rk3588-pcie3-phyMry{pclkhHophyk adisabledKaliases /mmc@fe2e0000 /serial@feb50000vcc12v-dcin-regulatorregulator-fixed vcc12v_dcin|Kvcc5v0-sys-regulatorregulator-fixed vcc5v0_sys|LK@LK@ Kvcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s3| Kchosen #serial2:1500000n8 compatibleinterrupt-parent#address-cells#size-cellsmodelcpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesphysphy-namespower-domainsstatusresetsreset-namesclock-names#phy-cellsrockchip,grfpinctrl-0pinctrl-namesdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreg-namesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csspi-max-frequencyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-nameregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-off-in-suspendregulator-always-onregulator-suspend-microvoltregulator-init-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellswakeup-sourcebitsrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfmmc0serial2vin-supplystdout-path