8$(  *,rockchip,rk3568-bpi-r2prorockchip,rk3568$7Bananapi-R2 Pro (RK3568) DDR4 Boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe2a0000/ethernet@fe010000/mmc@fe2b0000/mmc@fe310000cpus cpu@0cpu,arm,cortex-a55 !psci/Ccpu@100cpu,arm,cortex-a55!psci/C cpu@200cpu,arm,cortex-a55!psci/C cpu@300cpu,arm,cortex-a55!psci/C opp-table-0,operating-points-v2KCopp-408000000VQ ] 0k@opp-600000000V#F ] 0opp-816000000V0, ] 0|opp-1104000000VAʹ ] 0opp-1416000000VTfr ] 0opp-1608000000V_" ]0opp-1800000000VkI ]0opp-1992000000Vv ]000display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc protocol@14Copp-table-1,operating-points-v2CBopp-200000000V ] opp-300000000V] opp-400000000Vׄ] opp-600000000V#F] opp-700000000V)'] opp-800000000V/]B@hdmi-sound,simple-audio-cardHDMIi2sokaysimple-audio-card,codecsimple-audio-card,cpupmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0(smctimer,arm,armv8-timer0   %xin24m ,fixed-clock<n6Lxin24mCxin32k ,fixed-clock<Lxin32k_ idefaultsram@10f000 ,mmio-sram wsram@0,arm,scmi-shmemCsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@ ~satapmaliverxoob _ sata-phy disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci ~satapmaliverxoob ` sata-phyokayusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@  ~ref_clksuspend_clkbus_clkhost utmi_wide okay usb2-phyusb3-phyusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@  ~ref_clksuspend_clkbus_clkhost usb2-phyusb3-phy utmi_wide okayinterrupt-controller@fd400000 ,arm,gic-v3 @F  A(%Cusb@fd800000 ,generic-ehci  usbokayusb@fd840000 ,generic-ohci  usbokayusb@fd880000 ,generic-ehci  usbokayusb@fd8c0000 ,generic-ohci  usbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdCio-domains&,rockchip,rk3568-pmu-io-voltage-domainokay4BP^lzsyscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconCsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdCsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconCsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconCsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconCsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀCclock-controller@fdd00000,rockchip,rk3568-pmucruCclock-controller@fdd20000,rockchip,rk3568-cru ~xin24m  G C i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c . - ~i2cpclk_idefault okaypmic@20,rockchip,rk809 idefault_ !'!3!?!K!W!c!o!{!regulatorsDCDC_REG1 vdd_logic pqregulator-state-mem&DCDC_REG2vdd_gpu pqCCregulator-state-mem&DCDC_REG3vcc_ddrregulator-state-mem?DCDC_REG4vdd_npu pqregulator-state-mem&DCDC_REG5vcc_1v8w@w@Cregulator-state-mem&LDO_REG1vdda0v9_image  CWregulator-state-mem&LDO_REG2 vdda_0v9  regulator-state-mem&LDO_REG3 vdda0v9_pmu  regulator-state-mem?W LDO_REG4 vccio_acodec2Z2ZCregulator-state-mem&LDO_REG5 vccio_sdw@2ZCregulator-state-mem&LDO_REG6 vcc3v3_pmu2Z2ZCregulator-state-mem?W2ZLDO_REG7 vcca_1v8w@w@Cregulator-state-mem&LDO_REG8 vcca1v8_pmuw@w@regulator-state-mem?Ww@LDO_REG9vcca1v8_imagew@w@CXregulator-state-mem&SWITCH_REG1vcc_3v3Cregulator-state-mem&SWITCH_REG2 vcc3v3_sdC`regulator-state-mem&serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t  ,~baudclkapb_pclks""_#idefaultx disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 ~pwmpclk_$idefault disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 ~pwmpclk_%idefault disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm   0 ~pwmpclk_&idefault disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0  0 ~pwmpclk_'idefault disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller Cpower-domain@7  (power-domain@8  )*+power-domain@9   ,-.power-domain@10  /01234power-domain@11  5power-domain@13  6power-domain@14  789power-domain@15  :;<=>?@Agpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' jobmmugpu  ~gpubus/BokayCCvideo-codec@fdea0400,rockchip,rk3568-vpu vdpu  ~aclkhclkD iommu@fdea0800,rockchip,rk3568-iommu@  ~aclkiface  CDrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga Z ~aclkhclksclk & $ % coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu @  ~aclkhclkE iommu@fdee0800,rockchip,rk3568-iommu@ ?  ~aclkiface CEmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d   ~biuciuciu-driveciu-sampleр reset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a macirqeth_wake_irq@     W~stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref  stmmaceth F+G>HQokay    ZoutputgIrrgmiiidefault_JKLMN {O N </mdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22CIstmmac-axi-configCFrx-queues-configCGqueue0tx-queues-configCHqueue0vop@fe040000 0@vopgamma-lut ( %~aclkhclkdclk_vp0dclk_vp1dclk_vp2P okay,rockchip,rk3568-vop  ports Cport@0 endpoint@2(QCYport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >?   ~aclkifaceokayCPdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi D~pclk dphyR apb  disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi E~pclk dphyS apb  disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  -( ( ~iahbisfrcecrefidefault _TUV x8okayIWYXCports port@0endpoint(YCQport@1endpoint(ZCqos@fe128000,rockchip,rk3568-qossyscon C(qos@fe138080,rockchip,rk3568-qossyscon C7qos@fe138100,rockchip,rk3568-qossyscon C8qos@fe138180,rockchip,rk3568-qossyscon C9qos@fe148000,rockchip,rk3568-qossyscon C)qos@fe148080,rockchip,rk3568-qossyscon C*qos@fe148100,rockchip,rk3568-qossyscon C+qos@fe150000,rockchip,rk3568-qossyscon C5qos@fe158000,rockchip,rk3568-qossyscon C/qos@fe158100,rockchip,rk3568-qossyscon C0qos@fe158180,rockchip,rk3568-qossyscon C1qos@fe158200,rockchip,rk3568-qossyscon C2qos@fe158280,rockchip,rk3568-qossyscon C3qos@fe158300,rockchip,rk3568-qossyscon C4qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon C:qos@fe190280,rockchip,rk3568-qossyscon C>qos@fe190300,rockchip,rk3568-qossyscon C?qos@fe190380,rockchip,rk3568-qossyscon C@qos@fe190400,rockchip,rk3568-qossyscon CAqos@fe198000,rockchip,rk3568-qossyscon C6qos@fe1a8000,rockchip,rk3568-qossyscon C,qos@fe1a8080,rockchip,rk3568-qossyscon C-qos@fe1a8100,rockchip,rk3568-qossyscon C.pcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<KJIHGsyspmcmsglegacyerri( $~aclk_mstaclk_slvaclk_dbipclkauxpcis`[[[[ pcie-phyTw @@ pipe  disabledlegacy-interrupt-controller HC[mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b   ~biuciuciu-driveciu-sampleр resetokay idefault_\]^_!`-mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c   ~biuciuciu-driveciu-sampleр reset disabledspi@fe300000 ,rockchip,sfc0@ e x v~clk_sfchclk_sfc_aidefault disabledmmc@fe310000,rockchip,rk3568-dwcmshc1  { } n6( | z y { }~corebusaxiblocktimerokay :idefault_bcdei2s@fe400000,rockchip,rk3568-i2s-tdm@ 4 = AFqFq ? C 9~mclk_txmclk_rxhclksfHtx P Q tx-mrx-m8okayCi2s@fe410000,rockchip,rk3568-i2s-tdmA 5 E IFqFq G K :~mclk_txmclk_rxhclksffHrxtx R S tx-mrx-midefault0_ghijklmnopqr8 disabledi2s@fe420000,rockchip,rk3568-i2s-tdmB 6 MFq O O ;~mclk_txmclk_rxhclksffHtxrx Ttx-midefault_stuv8 disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC 7 S W <~mclk_txmclk_rxhclksffHtxrx U V tx-mrx-m8 disabledpdm@fe440000,rockchip,rk3568-pdmD L Z Y~pdm_clkpdm_hclksf Hrx_wxyz{|idefault Xpdm-m8 disabledspdif@fe460000,rockchip,rk3568-spdifF f ~mclkhclk _ \sfHtxidefault_}8 disableddma-controller@fe530000,arm,pl330arm,primecellS@ R   ~apb_pclkiC"dma-controller@fe550000,arm,pl330arm,primecellU@R   ~apb_pclkiCfi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ / H G ~i2cpclk_~idefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0 J I ~i2cpclk_idefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1 L K ~i2cpclk_idefault okayrtc@51,haoyu,hym8563Q Lrtcic_32koutidefault_i2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2 N M ~i2cpclk_idefault  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3 P O ~i2cpclk_idefault  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`    ~tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia g R Q~spiclkapb_pclks""Htxrxidefault _  disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib h T S~spiclkapb_pclks""Htxrxidefault _  disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic i V U~spiclkapb_pclks""Htxrxidefault _  disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid j X W~spiclkapb_pclks""Htxrxidefault_  disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte u  ~baudclkapb_pclks""_idefaultx disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v #  ~baudclkapb_pclks""_idefaultxokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w ' $~baudclkapb_pclks""_idefaultx disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x + (~baudclkapb_pclks"" _idefaultx disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y / ,~baudclkapb_pclks" " _idefaultx disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z 3 0~baudclkapb_pclks" " _idefaultx disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk { 7 4~baudclkapb_pclks""_idefaultx disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl | ; 8~baudclkapb_pclks""_idefaultx disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm } ? <~baudclkapb_pclks""_idefaultx disabledthermal-zonescpu-thermaltdtripscpu_alert0ppassiveCcpu_alert1$passivecpu_crits criticalcooling-mapsmap00 gpu-thermalttripsgpu-thresholdppassivegpu-target$passiveCgpu-crits criticalcooling-mapsmap0 tsadc@fe710000,rockchip,rk3568-tsadcq s  f@ `  ~tsadcapb_pclk   siinitdefaultsleep_okay  +Csaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]  ~saradcapb_pclk  saradc-apb Fokay Xpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y ~pwmpclk_idefault disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y ~pwmpclk_idefault disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn  Z Y ~pwmpclk_idefault disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0 Z Y ~pwmpclk_idefault disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ ~pwmpclk_idefaultokaypwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ ~pwmpclk_idefault disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo  ] \ ~pwmpclk_idefault disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0 ] \ ~pwmpclk_idefault disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ ~pwmpclk_idefault disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ ~pwmpclk_idefault disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp  ` _ ~pwmpclk_idefault disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0 ` _ ~pwmpclk_idefault disabledphy@fe830000,rockchip,rk3568-naneng-combphy " }  ~refapbpipe"  d v okayCphy@fe840000,rockchip,rk3568-naneng-combphy % ~  ~refapbpipe%  d v okayCphy@fe870000,rockchip,rk3568-csi-dphy y~pclk  apb disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy ~refpclk  z  apb  disabledCRmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy ~refpclk  {  apb  disabledCSusb2phy@fe8a0000,rockchip,rk3568-usb2phy ~phyclkLclk_usbphy0_480m  okayhost-port okay Cotg-port okay Cusb2phy@fe8b0000,rockchip,rk3568-usb2phy ~phyclkLclk_usbphy1_480m  okayhost-port okayCotg-port okayCpinctrl,rockchip,rk3568-pinctrl  wCgpio@fdd60000,rockchip,gpio-bank ! .    Cgpio@fe740000,rockchip,gpio-bankt " c d   gpio@fe750000,rockchip,gpio-banku # e f  @  Cgpio@fe760000,rockchip,gpio-bankv $ g h  `  COgpio@fe770000,rockchip,gpio-bankw % i j   pcfg-pull-up Cpcfg-pull-none Cpcfg-pull-none-drv-level-1  Cpcfg-pull-none-drv-level-2  Cpcfg-pull-none-drv-level-3  Cpcfg-pull-none-drv-level-5  Cpcfg-pull-up-drv-level-1  Cpcfg-pull-up-drv-level-2  Cpcfg-pull-none-smt  Cacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 %C cpuebcedpdpemmcemmc-bus8 %  Cbemmc-clk %Ccemmc-cmd %Cdemmc-datastrobe %Ceeth0eth1flashfspifspi-pins` %Cagmac0gmac0-miim %Cgmac0-rx-bus20 %Cgmac0-tx-bus20 %   Cgmac0-rgmii-clk %Cgmac0-rgmii-bus@ %Cgmac1gmac1m1-miim %CJgmac1m1-rx-bus20 % CLgmac1m1-tx-bus20 %CKgmac1m1-rgmii-clk %CMgmac1m1-rgmii-bus@ %CNgpuhdmitxhdmitxm0-cec %CVhdmitx-scl %CThdmitx-sda %CUi2c0i2c0-xfer %  Ci2c1i2c1-xfer %  C~i2c2i2c2m0-xfer % Ci2c3i2c3m0-xfer %Ci2c4i2c4m0-xfer %  Ci2c5i2c5m0-xfer %  Ci2s1i2s1m0-lrckrx %Cji2s1m0-lrcktx %Cii2s1m0-sclkrx %Chi2s1m0-sclktx %Cgi2s1m0-sdi0 % Cki2s1m0-sdi1 % Cli2s1m0-sdi2 % Cmi2s1m0-sdi3 %Cni2s1m0-sdo0 %Coi2s1m0-sdo1 %Cpi2s1m0-sdo2 % Cqi2s1m0-sdo3 % Cri2s2i2s2m0-lrcktx %Cti2s2m0-sclktx %Csi2s2m0-sdi %Cui2s2m0-sdo %Cvi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk %Cwpdmm0-clk1 %Cxpdmm0-sdi0 % Cypdmm0-sdi1 % Czpdmm0-sdi2 % C{pdmm0-sdi3 %C|pmicpmic_int %C pmupwm0pwm0m0-pins %C$pwm1pwm1m0-pins %C%pwm2pwm2m0-pins %C&pwm3pwm3-pins %C'pwm4pwm4-pins %Cpwm5pwm5-pins %Cpwm6pwm6-pins %Cpwm7pwm7-pins %Cpwm8pwm8m0-pins % Cpwm9pwm9m0-pins % Cpwm10pwm10m0-pins % Cpwm11pwm11m0-pins %Cpwm12pwm12m1-pins %Cpwm13pwm13m1-pins %Cpwm14pwm14m1-pins %Cpwm15pwm15m1-pins %Crefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ %C\sdmmc0-clk %C]sdmmc0-cmd %C^sdmmc0-det %C_sdmmc1sdmmc2spdifspdifm0-tx %C}spi0spi0m0-pins0 % Cspi0m0-cs0 %Cspi0m0-cs1 %Cspi1spi1m0-pins0 % Cspi1m0-cs0 %Cspi1m0-cs1 %Cspi2spi2m0-pins0 %Cspi2m0-cs0 %Cspi2m0-cs1 %Cspi3spi3m1-pins0 %Ctsadctsadc-shutorg %Ctsadc-pin %Cuart0uart0-xfer %C#uart1uart1m0-xfer %  Cuart2uart2m0-xfer %Cuart3uart3m0-xfer %Cuart4uart4m0-xfer %Cuart5uart5m0-xfer %Cuart6uart6m0-xfer %Cuart7uart7m1-xfer %Cuart8uart8m0-xfer %Cuart9uart9m1-xfer %Cvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2ledsblue-led-pin %Cgreen-led-pin %Chym8563hym8563-int %Cir-receiverir-receiver-pin %Cpcieminipcie-enable-h %Cngffpcie-enable-h %Cminipcie-reset-h %Cngffpcie-reset-h %Cusbvcc5v0_usb_host_en %Cvcc5v0_usb_otg_en %Csata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci ~satapmaliverxoob ^ sata-phy disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconCqos@fe190080,rockchip,rk3568-qossyscon C;qos@fe190100,rockchip,rk3568-qossyscon C<qos@fe190200,rockchip,rk3568-qossyscon C=syscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconˀCphy@fe8c0000,rockchip,rk3568-pcie3-phy  &' w~refclk_mrefclk_npclk phy 3okay D Cpcie@fe270000,rockchip,rk3568-pcie i( $~aclk_mstaclk_slvaclk_dbipclkauxpci<syspmcmsglegacyerrs` pcie-phy0@@'Tw @@@dbiapbconfig pipeokayidefault_ OO [legacy-interrupt-controller Cpcie@fe280000,rockchip,rk3568-pcie i( $~aclk_mstaclk_slvaclk_dbipclkauxpci<syspmcmsglegacyerrs`  pcie-phy0@(Tw @@dbiapbconfig pipeokayidefault_ O [legacy-interrupt-controller Cethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a*macirqeth_wake_irq@     W~stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref  stmmaceth +>Qokay    Zinputrrgmiiidefault_ {O N OCmdio,snps,dwmac-mdio switch@1f,mediatek,mt7531ports port@1 klan0port@2 klan1port@3 klan2port@4 klan3port@5 kcpu qrrgmiifixed-link z stmmac-axi-configCrx-queues-configCqueue0tx-queues-configCqueue0fixed-link z phy@fe820000,rockchip,rk3568-naneng-combphy  |  ~refapbpipe  d v okayCchosen serial2:1500000n8leds ,gpio-ledsidefault_led-0  off status led-1  on power dc-12v-regulator,regulator-fixeddc_12vChdmi-con,hdmi-connectoraportendpoint(CZir-receiver,gpio-ir-receiver idefault_vcc3v3-sys-regulator,regulator-fixed vcc3v3_sys2Z2Z C!vcc5v0-sys-regulator,regulator-fixed vcc5v0_sysLK@LK@ Cpcie30-avdd0v9-regulator,regulator-fixedpcie30_avdd0v9   !pcie30-avdd1v8-regulator,regulator-fixedpcie30_avdd1v8w@w@ !vcc3v3-pi6c-05-regulator,regulator-fixed vcc3v3_pcie2Z2Z    @ Cvcc3v3-minipcie-regulator,regulator-fixedvcc3v3_minipcie2Z2Z  idefault_ P Cvcc3v3-ngff-regulator,regulator-fixed vcc3v3_ngff2Z2Z  idefault_ P Cvcc5v0-usb-regulator,regulator-fixed vcc5v0_usbLK@LK@ Cvcc5v0-usb-host-regulator,regulator-fixed  idefault_vcc5v0_usb_hostLK@LK@ Cvcc5v0-usb-otg-regulator,regulator-fixed  idefault_vcc5v0_usb_otgLK@LK@ C interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2phandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grfrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaysnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplybus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplyrockchip,pmugpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfdata-lanesreset-gpiosvpcie3v3-supplylabelethernetfull-duplexpausestdout-pathcolordefault-statefunctionvin-supplyenable-active-highstartup-delay-us