m8f(frockchip,r88rockchip,rk3368 + 7Rockchip R88aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0d0000/mmc@ff0f0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53psciarm-pmuarm,armv8-pmuv3`pqrstuvw  psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clockn6 xin24m Dmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @-р ;  D r vBbiuciuciu-driveciu-sampleN Y `reset ldisabledmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @-р ;  E s wBbiuciuciu-driveciu-sampleN !Y `resetlokays E  default   mmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@-р ;  G u yBbiuciuciu-driveciu-sampleN #Y `resetlokay"default saradc@ff100000rockchip,saradc $4; I [Bsaradcapb_pclkY W `saradc-apblokayFspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi; A RBspiclkapb_pclk ,default+ ldisabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi; B SBspiclkapb_pclk -default+ ldisabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi; C TBspiclkapb_pclk )default !+ ldisabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+Bi2c; Ndefault" ldisabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+Bi2c; Odefault# ldisabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+Bi2c; Pdefault$ ldisabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+Bi2c; Qdefault% ldisabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartn6; M UBbaudclkapb_pclk 7R\ ldisabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartn6; N VBbaudclkapb_pclk 8R\ ldisabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartn6; P XBbaudclkapb_pclk :R\ ldisabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartn6; Q YBbaudclkapb_pclk ;R\ ldisableddma-controller@ff250000arm,pl330arm,primecell%@it;  Bapb_pclkthermal-zonescpu-thermald&tripscpu_alert0$passive'cpu_alert18passive(cpu_crits criticalcooling-mapsmap0'0map1(0 gpu-thermald&tripsgpu_alert08passive)gpu_crit8 criticalcooling-mapsmap0)0tsadc@ff280000rockchip,rk3368-tsadc( %; H ZBtsadcapb_pclkY  `tsadc-apbinitdefaultsleep*+*/slokayF]&ethernet@ff290000rockchip,rk3368-gmac) xmacirq,8;  f g c ]MBstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_maclokay-rmiioutput .  'B@default/0usb@ff500000 generic-ehciP ; lokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X ; Botghost ,@@ lokaydma-controller@ff600000arm,pl330arm,primecell`@it;  Bapb_pclkEi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ce; LBi2c <default0+lokaysyr827@40silergy,syr827@;Xvdd_cpug, 4`@1rtc@51haoyu,hym8563Q  xin32kUi2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+Bi2c; Mdefault2 ldisabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault3; _ ldisabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault4; _ ldisabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh ; _ ldisabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default5; _ ldisabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uarti; O WBbaudclkapb_pclk 9default6R\lokaymbox@ff6b0000rockchip,rk3368-mailboxk0; E Bpclk_mailbox ldisabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdspower-controller!rockchip,rk3368-power-controller+Hpower-domain@12 ;       c h g n o r s f d d h i l k j n m$$789:;<=>?power-domain@14 ;  o p $@ABpower-domain@16; @$Csyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdsIio-domains&rockchip,rk3368-pmu-io-voltage-domainlokay+6reboot-modesyscon-reboot-modeAHRBTRBbRB rRBclock-controller@ff760000rockchip,rk3368-cruv;DBxin24m, ~ syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw,io-domains"rockchip,rk3368-io-voltage-domainlokaywatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt; p Olokaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  B; a U Bpclktimerspdif@ff880000rockchip,rk3368-spdif 6; S  BmclkhclkEtxdefaultF ldisabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (Bi2s_clki2s_hclk; T EEtxrx ldisabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5Bi2s_clki2s_hclk; R EEtxrxdefaultG ldisablediommu@ff900800rockchip,iommu ;  BaclkifaceH  ldisablediommu@ff914000rockchip,iommu @P ;  BaclkifaceH  ldisablediommu@ff930300rockchip,iommu ;  BaclkifaceH  ldisablediommu@ff9a0440rockchip,iommu @@@ ;  Baclkiface ldisablediommu@ff9a0800rockchip,iommu  ;  Baclkiface ldisabledqos@ffad0000rockchip,rk3368-qossyscon 7qos@ffad0080rockchip,rk3368-qossyscon 8qos@ffad0100rockchip,rk3368-qossyscon 9qos@ffad0180rockchip,rk3368-qossyscon :qos@ffad0200rockchip,rk3368-qossyscon ;qos@ffad0280rockchip,rk3368-qossyscon <qos@ffad0300rockchip,rk3368-qossyscon =qos@ffad0380rockchip,rk3368-qossyscon >qos@ffad0400rockchip,rk3368-qossyscon ?qos@ffae0000rockchip,rk3368-qossyscon @qos@ffae0100rockchip,rk3368-qossyscon Aqos@ffae0180rockchip,rk3368-qossyscon Bqos@ffaf0000rockchip,rk3368-qossyscon Cefuse@ffb00000rockchip,rk3368-efuse +; q Bpclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400@ @ `   pinctrlrockchip,rk3368-pinctrl,-I+:gpio@ff750000rockchip,gpio-banku; @ QAQRgpio@ff780000rockchip,gpio-bankx; A RAQgpio@ff790000rockchip,gpio-banky; B SAQPgpio@ff7a0000rockchip,gpio-bankz; C TAQ.pcfg-pull-up]Lpcfg-pull-downjpcfg-pull-noneyMpcfg-pull-none-12may Nemmcemmc-clkJemmc-cmdKemmc-pwrLemmc-bus1Lemmc-bus4@LLLLemmc-bus8KKKKKKKKemmc-resetMOgmacrgmii-pinsMMMN N NNN NMMMMMMrmii-pinsMMMN N NMMMM/i2c0i2c0-xfer MM0i2c1i2c1-xfer MM2i2c2i2c2-xfer  MM"i2c3i2c3-xfer MM#i2c4i2c4-xfer MM$i2c5i2c5-xfer MM%i2si2s-8ch-bus M MMMMMMMMGpwm0pwm0-pinM3pwm1pwm1-pinM4pwm3pwm3-pinM5sdio0sdio0-bus1Lsdio0-bus4@LLLLsdio0-cmdL sdio0-clkM sdio0-cdLsdio0-wpLsdio0-pwrLsdio0-bkpwrLsdio0-intLsdmmcsdmmc-clk Msdmmc-cmd Lsdmmc-cd Lsdmmc-bus1Lsdmmc-bus4@LLLLspdifspdif-txMFspi0spi0-clkLspi0-cs0Lspi0-cs1Lspi0-txLspi0-rxLspi1spi1-clkLspi1-cs0Lspi1-cs1Lspi1-rxLspi1-txLspi2spi2-clk Lspi2-cs0 L!spi2-rx L spi2-tx Ltsadcotp-pinM*otp-outM+uart0uart0-xfer LMuart0-ctsMuart0-rtsMuart1uart1-xfer LMuart1-ctsMuart1-rtsMuart2uart2-xfer LM6uart3uart3-xfer LMuart3-ctsMuart3-rtsMuart4uart4-xfer LMuart4-ctsMuart4-rtsMpcfg-pull-none-drv-8mayJpcfg-pull-up-drv-8ma]Kirir-intLTkeyspwr-keyLQledsstby-pwren Mled-ctlMSsdiowifi-reg-onMWbt-rstMVusbhost-vbus-drvMXchosenserial2:115200n8memorymemory@emmc-pwrseqmmc-pwrseq-emmcOdefault Pgpio-keys gpio-keysdefaultQkey-power R GPIO Powertgpio-leds gpio-ledsled-0 .r88:green:leddefaultSir-receivergpio-ir-receiver .defaultTsdio-pwrseqmmc-pwrseq-simple;U Bext_clockdefaultVW.. vcc18-regulatorregulator-fixedXvcc_18w@w@1vcc-host-regulatorregulator-fixed RdefaultX Xvcc_host1vcc-io-regulatorregulator-fixedXvcc_io2Z2Z1vcc-lan-regulatorregulator-fixedXvcc_lan2Z2Z-vcc-sys-regulatorregulator-fixedXvcc_sysLK@LK@1vccio-wl-regulatorregulator-fixed Xvccio_wl2Z2Zvdd-10-regulatorregulator-fixedXvdd_10B@B@1 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusassigned-clocksassigned-clock-parentsbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeed#io-channel-cellsvref-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cells#power-domain-cellspm_qospmu-supplyvop-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsaudio-supplygpio30-supplygpio1830-supplywifi-supplydmasdma-namespower-domains#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codeenable-active-high