a8d( ,pine64,rock64rockchip,rk3328 +7Pine64 Rock64aliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci  cpu@1cpuarm,cortex-a53xpsci  cpu@2cpuarm,cortex-a53xpsci  cpu@3cpuarm,cortex-a53xpsci  idle-statespscicpu-sleeparm,idle-state*;Rxcsl2-cache0cacheopp-table-0operating-points-v2opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @analog-soundsimple-audio-cardi2sAnalog%okaysimple-audio-card,cpu,simple-audio-card,codec,arm-pmuarm,cortex-a53-pmu06defgA display-subsystemrockchip,display-subsystemT hdmi-soundsimple-audio-cardi2sHDMI%okaysimple-audio-card,cpu,simple-audio-card,codec,psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer06   xin24m fixed-clockZgn6wxin24mEi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s 6)7i2s_clki2s_hclk  txrx%okayi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s 6*8i2s_clki2s_hclktxrx%okayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s 6+9i2s_clki2s_hclktxrx %disabledspdif@ff030000rockchip,rk3328-spdif 6.: mclkhclk txdefault%okayhpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep %disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd9io-domains"rockchip,rk3328-io-voltage-domain%okay,gpiorockchip,rk3328-grf-gpio9IDpower-controller!rockchip,rk3328-power-controllerU+;power-domain@6Upower-domain@5 BABUpower-domain@8FUreboot-modesyscon-reboot-modeipRB|RBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 67&baudclkapb_pclktxrxdefault  ! %disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 68'baudclkapb_pclktxrxdefault "#$ %disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 69(baudclkapb_pclktxrxdefault%%okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c 6$+7 i2cpclkdefault& %disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c 6%+8 i2cpclkdefault'%okaypmic@18rockchip,rk805 (6Zwxin32krk805-clkout29Idefault)****(*gregulatorsDCDC_REG1 4vdd_logicC 4[ s0regulator-state-memB@DCDC_REG24vdd_armC 4[ s0regulator-state-mem~DCDC_REG34vcc_ddrregulator-state-memDCDC_REG44vcc_ioC2Z[2Zregulator-state-mem2ZLDO_REG14vcc_18Cw@[w@regulator-state-memw@LDO_REG2 4vcc18_emmcCw@[w@regulator-state-memw@LDO_REG34vdd_10CB@[B@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c 6&+9 i2cpclkdefault+ %disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c 6'+: i2cpclkdefault, %disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 61+ spiclkapb_pclk txrxdefault-./0%okayflash@0jedec,spi-norwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt 6(pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault1 %disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault2 %disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault3 %disabledpwm@ff1b0030rockchip,rk3328-pwm0 62< pwmpclkdefault4 %disableddma-controller@ff1f0000arm,pl330arm,primecell@6 apb_pclkthermal-zonessoc-thermal!7EW5tripstrip-point0gpspassivetrip-point1gLspassive6soc-critgss criticalcooling-mapsmap0~60 tsadc@ff250000rockchip,rk3328-tsadc% 6:$P$tsadcapb_pclkinitdefaultsleep787B tsadc-apb9%okay25efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuseM id@7cpu-leakage@17logic-leakage@19cpu-version@1aaFadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( 6Pf%saradcapb_pclkV saradc-apb %disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500T6ZW]XY[\"xgpgpmmupppp0ppmmu0pp1ppmmu1 buscorefiommu@ff330200rockchip,iommu3 6` aclkiface %disablediommu@ff340800rockchip,iommu4@ 6bF aclkiface %disabledvideo-codec@ff350000rockchip,rk3328-vpu5 6 xvdpuF aclkhclk:;iommu@ff350800rockchip,iommu5@ 6 F aclkiface;:video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6 6 BABaxiahbcabaccoreAB ׄׄ<;iommu@ff360480rockchip,iommu 6@6@ 6JB aclkiface;<vop@ff370000rockchip,rk3328-vop7> 6 x;aclk_vopdclk_vophclk_vop axiahbdclk=%okayport+ endpoint@0>Ciommu@ff373f00rockchip,iommu7? 6 ; aclkiface%okay=hdmi@ff3c0000rockchip,rk3328-dw-hdmi<6#GFiahbisfrcec?hdmidefault @AB9%okayports+port@0endpointC>port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk9%okay Dphy@ff430000rockchip,rk3328-hdmi-phyC 6SEysysclkrefoclkrefpclk whdmi_phyZF cpu-version%okay?clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD9Zx=&'(ABDC"\5H4$ zEEE|n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyEphyclk wusb480m_phyZ{ G%okayGotg-port$6;<=xotg-bvalidotg-idlinestate%okayVhost-port 6> xlinestate%okayWmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ 6  =!JNbiuciuciu-driveciu-sample р%okay+5GXdefaultHIJKcLmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ 6  >"KObiuciuciu-driveciu-sample р %disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ 6 ?#LPbiuciuciu-driveciu-sample р%okay+5o~default MNOcethernet@ff540000rockchip,rk3328-gmacT 6xmacirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth9%okaydf PPinputrgmiidefaultQ R 'P$$ethernet@ff550000rockchip,rk3328-gmacU9 6xmacirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb stmmacethrmii-Soutput %disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultTU8Susb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X 6MotgJhostRds@ V usb2-phy%okayusb@ff5c0000 generic-ehci\ 6 NGWusb%okayusb@ff5d0000 generic-ohci] 6 NGWusb%okayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` 6C`aref_clksuspend_clkbus_clkJhost utmi_wide  %okayinterrupt-controller@ff811000 arm,gic-400 9 J@ @ `  6 crypto@ff060000rockchip,rk3328-crypto@ 6PQ;hclk_masterhclk_slavesclkD crypto-rstpinctrlrockchip,rk3328-pinctrl9+ _gpio@ff210000rockchip,gpio-bank! 639I J 9cgpio@ff220000rockchip,gpio-bank" 649I J 9Rgpio@ff230000rockchip,gpio-bank# 659I J 9(gpio@ff240000rockchip,gpio-bank$ 669I J 9pcfg-pull-up fZpcfg-pull-down sbpcfg-pull-none Xpcfg-pull-none-2ma  apcfg-pull-up-2ma f pcfg-pull-up-4ma f [pcfg-pull-none-4ma  ^pcfg-pull-down-4ma s pcfg-pull-none-8ma  \pcfg-pull-up-8ma f ]pcfg-pull-none-12ma  _pcfg-pull-up-12ma f `pcfg-output-high pcfg-output-low pcfg-input-high f Ypcfg-input i2c0i2c0-xfer XX&i2c1i2c1-xfer XX'i2c2i2c2-xfer  XX+i2c3i2c3-xfer XX,i2c3-pins XXhdmi_i2chdmii2c-xfer XXApdm-0pdmm0-clk Xpdmm0-fsync Xpdmm0-sdi0 Xpdmm0-sdi1 Xpdmm0-sdi2 Xpdmm0-sdi3 Xpdmm0-clk-sleep Ypdmm0-sdi0-sleep Ypdmm0-sdi1-sleep Ypdmm0-sdi2-sleep Ypdmm0-sdi3-sleep Ypdmm0-fsync-sleep Ytsadcotp-pin  X7otp-out  X8uart0uart0-xfer  XZuart0-cts  X uart0-rts  X!uart0-rts-pin  Xuart1uart1-xfer XZ"uart1-cts X#uart1-rts X$uart1-rts-pin Xuart2-0uart2m0-xfer XZuart2-1uart2m1-xfer XZ%spi0-0spi0m0-clk Zspi0m0-cs0  Zspi0m0-tx  Zspi0m0-rx  Zspi0m0-cs1  Zspi0-1spi0m1-clk Zspi0m1-cs0 Zspi0m1-tx Zspi0m1-rx Zspi0m1-cs1 Zspi0-2spi0m2-clk Z-spi0m2-cs0 Z0spi0m2-tx Z.spi0m2-rx Z/i2s1i2s1-mclk Xi2s1-sclk Xi2s1-lrckrx Xi2s1-lrcktx Xi2s1-sdi Xi2s1-sdo Xi2s1-sdio1 Xi2s1-sdio2 Xi2s1-sdio3 Xi2s1-sleep YYYYYYYYYi2s2-0i2s2m0-mclk Xi2s2m0-sclk Xi2s2m0-lrckrx Xi2s2m0-lrcktx Xi2s2m0-sdi Xi2s2m0-sdo Xi2s2m0-sleep` YYYYYYi2s2-1i2s2m1-mclk Xi2s2m1-sclk Xi2sm1-lrckrx Xi2s2m1-lrcktx Xi2s2m1-sdi Xi2s2m1-sdo Xi2s2m1-sleepP YYYYYspdif-0spdifm0-tx Xspdif-1spdifm1-tx Xspdif-2spdifm2-tx Xsdmmc0-0sdmmc0m0-pwren [sdmmc0m0-pin [sdmmc0-1sdmmc0m1-pwren [sdmmc0m1-pin [dsdmmc0sdmmc0-clk \Hsdmmc0-cmd ]Isdmmc0-dectn [Jsdmmc0-wrprt [sdmmc0-bus1 ]sdmmc0-bus4@ ]]]]Ksdmmc0-pins [[[[[[[[sdmmc0extsdmmc0ext-clk ^sdmmc0ext-cmd [sdmmc0ext-wrprt [sdmmc0ext-dectn [sdmmc0ext-bus1 [sdmmc0ext-bus4@ [[[[sdmmc0ext-pins [[[[[[[[sdmmc1sdmmc1-clk  \sdmmc1-cmd  ]sdmmc1-pwren ]sdmmc1-wrprt ]sdmmc1-dectn ]sdmmc1-bus1 ]sdmmc1-bus4@ ]]]]sdmmc1-pins  [ [[[[[[[[emmcemmc-clk _Memmc-cmd `Nemmc-pwren Xemmc-rstnout Xemmc-bus1 `emmc-bus4@ ````emmc-bus8 ````````Opwm0pwm0-pin X1pwm1pwm1-pin X2pwm2pwm2-pin X3pwmirpwmir-pin X4gmac-1rgmiim1-pins`  \ ^^\^^^ ^ ^\ \^^\\\ \^\\\\Qrmiim1-pins a_aaaa a a_ _ X XXXXXgmac2phyfephyled-speed10 Xfephyled-duplex Xfephyled-rxm1 XTfephyled-txm1 Xfephyled-linkm1 XUtsadc_pintsadc-int  Xtsadc-pin  Xhdmi_pinhdmi-cec X@hdmi-hpd bBcif-0dvp-d2d9-m0 XXXXX X X XXXXXcif-1dvp-d2d9-m1 XXXXXXXXXXXXirir-int Xfpmicpmic-int-l Z)usb2usb20-host-drv Xechosen serial2:1500000n8external-gmac-clock fixed-clockgsY@ wgmac_clkinZPsdmmc-regulatorregulator-fixed cdefaultd4vcc_sdC2Z[2Z Lvcc-host-5v-regulatorregulator-fixed cdefaulte 4vcc_host_5v *vcc-sysregulator-fixed4vcc_sysCLK@[LK@*ir-receivergpio-ir-receiver (fdefaultleds gpio-ledsled-0 g mmc0led-1 g heartbeatspdif-soundsimple-audio-cardSPDIFsimple-audio-card,cpu,hsimple-audio-card,codec,ispdif-ditlinux,spdif-diti compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltspi-max-frequency#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesmute-gpiosnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplymmc-hs200-1_8vnon-removablevqmmc-supplysnps,txpblclock_in_outphy-supplyphy-modesnps,force_thresh_dma_modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplylinux,default-trigger