8( Aradxa,rockpi-erockchip,rk3328 +7Radxa ROCK Pi Ealiases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci  cpu@1cpuarm,cortex-a53xpsci  cpu@2cpuarm,cortex-a53xpsci  cpu@3cpuarm,cortex-a53xpsci  idle-statespscicpu-sleeparm,idle-state*;Rxcsl2-cache0cacheopp-table-0operating-points-v2opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @analog-soundsimple-audio-cardi2sAnalog%okaysimple-audio-card,cpu,simple-audio-card,codec,arm-pmuarm,cortex-a53-pmu06defgA display-subsystemrockchip,display-subsystemT hdmi-soundsimple-audio-cardi2sHDMI %disabledsimple-audio-card,cpu,simple-audio-card,codec,psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer06   xin24m fixed-clockZgn6wxin24mDi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s 6)7i2s_clki2s_hclk  txrx %disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s 6*8i2s_clki2s_hclktxrx%okayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s 6+9i2s_clki2s_hclktxrx %disabledspdif@ff030000rockchip,rk3328-spdif 6.: mclkhclk txdefault %disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep %disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd8io-domains"rockchip,rk3328-io-voltage-domain%okay+gpiorockchip,rk3328-grf-gpio9Ipower-controller!rockchip,rk3328-power-controllerU+;power-domain@6Upower-domain@5 BABUpower-domain@8FUreboot-modesyscon-reboot-modeipRB|RBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 67&baudclkapb_pclktxrxdefault   %disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 68'baudclkapb_pclktxrxdefault !"# %disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 69(baudclkapb_pclktxrxdefault$%okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c 6$+7 i2cpclkdefault% %disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c 6%+8 i2cpclkdefault&%okaypmic@18rockchip,rk805 '6Zwxin32krk805-clkout29Idefault())))()regulatorsDCDC_REG14vdd_logCWi 4 0regulator-state-memB@DCDC_REG24vdd_armCWi 4 0regulator-state-mem~DCDC_REG34vcc_ddrCWregulator-state-memDCDC_REG44vcc_ioCWi2Z2Zregulator-state-mem2ZLDO_REG14vcc_18CWiw@w@9regulator-state-memw@LDO_REG2 4vcc18_emmcCWiw@w@regulator-state-memw@LDO_REG34vdd_10CWiB@B@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c 6&+9 i2cpclkdefault* %disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c 6'+: i2cpclkdefault+ %disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 61+ spiclkapb_pclk txrxdefault,-./ %disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt 6(pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault0 %disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault1 %disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault2 %disabledpwm@ff1b0030rockchip,rk3328-pwm0 62< pwmpclkdefault3 %disableddma-controller@ff1f0000arm,pl330arm,primecell@6 apb_pclkthermal-zonessoc-thermal%3E4tripstrip-point0Upapassivetrip-point1ULapassive5soc-critUsa criticalcooling-mapsmap0l50q tsadc@ff250000rockchip,rk3328-tsadc% 6:$P$tsadcapb_pclkinitdefaultsleep676B tsadc-apb8%okay4efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1aEadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( 6P"%saradcapb_pclkV saradc-apb%okay49egpu@ff300000"rockchip,rk3328-maliarm,mali-4500T6ZW]XY[\"@gpgpmmupppp0ppmmu0pp1ppmmu1 buscorefiommu@ff330200rockchip,iommu3 6` aclkifaceP %disablediommu@ff340800rockchip,iommu4@ 6bF aclkifaceP %disabledvideo-codec@ff350000rockchip,rk3328-vpu5 6 @vdpuF aclkhclk]:d;iommu@ff350800rockchip,iommu5@ 6 F aclkifacePd;:video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6 6 BABaxiahbcabaccoreAB ׄׄ]<d;iommu@ff360480rockchip,iommu 6@6@ 6JB aclkifacePd;<vop@ff370000rockchip,rk3328-vop7> 6 x;aclk_vopdclk_vophclk_vop axiahbdclk]= %disabledport+ endpoint@0r>Ciommu@ff373f00rockchip,iommu7? 6 ; aclkifaceP %disabled=hdmi@ff3c0000rockchip,rk3328-dw-hdmi<6#GFiahbisfrcec?hdmidefault @AB8 %disabledports+port@0endpointrC>port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk8%okayphy@ff430000rockchip,rk3328-hdmi-phyC 6SDysysclkrefoclkrefpclk whdmi_phyZE cpu-version %disabled?clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD8Zx=&'(ABDC"\5H4$zDDD|n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyDphyclk wusb480m_phyZ{F%okayFotg-port$6;<=@otg-bvalidotg-idlinestate %disabledXhost-port 6> @linestate%okayYmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ 6  =!JNbiuciuciu-driveciu-sampleр%okaydefaultGHIJKmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ 6  >"KObiuciuciu-driveciu-sampleр %disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ 6 ?#LPbiuciuciu-driveciu-sampleр%okay(:GVdefault LMNdethernet@ff540000rockchip,rk3328-gmacT 6@macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth8q%okaydfOO|inputPrgmiidefaultQ&mdiosnps,dwmac-mdio+ethernet-phy@1RSdefault T6'P TPethernet@ff550000rockchip,rk3328-gmacU8 6@macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb stmmacethrmiiUq|output%okaymdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultVWUusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X 6Motgotg(7@ X usb2-phy %disabledusb@ff5c0000 generic-ehci\ 6 NFYusb%okayusb@ff5d0000 generic-ohci] 6 NFYusb %disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3` 6C`aref_clksuspend_clkbus_clkhost Futmi_wideOp%okayinterrupt-controller@ff811000 arm,gic-400 @ @ `  6 crypto@ff060000rockchip,rk3328-crypto@ 6PQ;hclk_masterhclk_slavesclkD crypto-rstpinctrlrockchip,rk3328-pinctrl8+ #gpio@ff210000rockchip,gpio-bank! 639I hgpio@ff220000rockchip,gpio-bank" 649I Tgpio@ff230000rockchip,gpio-bank# 659I 'gpio@ff240000rockchip,gpio-bank$ 669I gpcfg-pull-up *\pcfg-pull-down 7dpcfg-pull-none FZpcfg-pull-none-2ma F Scpcfg-pull-up-2ma * Spcfg-pull-up-4ma * S]pcfg-pull-none-4ma F S`pcfg-pull-down-4ma 7 Spcfg-pull-none-8ma F S^pcfg-pull-up-8ma * S_pcfg-pull-none-12ma F S apcfg-pull-up-12ma * S bpcfg-output-high bpcfg-output-low npcfg-input-high * y[pcfg-input yi2c0i2c0-xfer ZZ%i2c1i2c1-xfer ZZ&i2c2i2c2-xfer  ZZ*i2c3i2c3-xfer ZZ+i2c3-pins ZZhdmi_i2chdmii2c-xfer ZZApdm-0pdmm0-clk Zpdmm0-fsync Zpdmm0-sdi0 Zpdmm0-sdi1 Zpdmm0-sdi2 Zpdmm0-sdi3 Zpdmm0-clk-sleep [pdmm0-sdi0-sleep [pdmm0-sdi1-sleep [pdmm0-sdi2-sleep [pdmm0-sdi3-sleep [pdmm0-fsync-sleep [tsadcotp-pin  Z6otp-out  Z7uart0uart0-xfer  Z\uart0-cts  Zuart0-rts  Z uart0-rts-pin  Zuart1uart1-xfer Z\!uart1-cts Z"uart1-rts Z#uart1-rts-pin Zuart2-0uart2m0-xfer Z\uart2-1uart2m1-xfer Z\$spi0-0spi0m0-clk \spi0m0-cs0  \spi0m0-tx  \spi0m0-rx  \spi0m0-cs1  \spi0-1spi0m1-clk \spi0m1-cs0 \spi0m1-tx \spi0m1-rx \spi0m1-cs1 \spi0-2spi0m2-clk \,spi0m2-cs0 \/spi0m2-tx \-spi0m2-rx \.i2s1i2s1-mclk Zi2s1-sclk Zi2s1-lrckrx Zi2s1-lrcktx Zi2s1-sdi Zi2s1-sdo Zi2s1-sdio1 Zi2s1-sdio2 Zi2s1-sdio3 Zi2s1-sleep [[[[[[[[[i2s2-0i2s2m0-mclk Zi2s2m0-sclk Zi2s2m0-lrckrx Zi2s2m0-lrcktx Zi2s2m0-sdi Zi2s2m0-sdo Zi2s2m0-sleep` [[[[[[i2s2-1i2s2m1-mclk Zi2s2m1-sclk Zi2sm1-lrckrx Zi2s2m1-lrcktx Zi2s2m1-sdi Zi2s2m1-sdo Zi2s2m1-sleepP [[[[[spdif-0spdifm0-tx Zspdif-1spdifm1-tx Zspdif-2spdifm2-tx Zsdmmc0-0sdmmc0m0-pwren ]sdmmc0m0-pin ]sdmmc0-1sdmmc0m1-pwren ]sdmmc0m1-pin ]isdmmc0sdmmc0-clk ^Gsdmmc0-cmd _Hsdmmc0-dectn ]Isdmmc0-wrprt ]sdmmc0-bus1 _sdmmc0-bus4@ ____Jsdmmc0-pins ]]]]]]]]sdmmc0extsdmmc0ext-clk `sdmmc0ext-cmd ]sdmmc0ext-wrprt ]sdmmc0ext-dectn ]sdmmc0ext-bus1 ]sdmmc0ext-bus4@ ]]]]sdmmc0ext-pins ]]]]]]]]sdmmc1sdmmc1-clk  ^sdmmc1-cmd  _sdmmc1-pwren _sdmmc1-wrprt _sdmmc1-dectn _sdmmc1-bus1 _sdmmc1-bus4@ ____sdmmc1-pins  ] ]]]]]]]]emmcemmc-clk aLemmc-cmd bMemmc-pwren Zemmc-rstnout Zemmc-bus1 bemmc-bus4@ bbbbemmc-bus8 bbbbbbbbNpwm0pwm0-pin Z0pwm1pwm1-pin Z1pwm2pwm2-pin Z2pwmirpwmir-pin Z3gmac-1rgmiim1-pins`  ^ ``^``` ` `^ ^``^^^ ^`^^^^Qrmiim1-pins cacccc c ca a Z ZZZZZgmac2phyfephyled-speed10 Zfephyled-duplex Zfephyled-rxm1 ZVfephyled-txm1 Zfephyled-linkm1 ZWtsadc_pintsadc-int  Ztsadc-pin  Zhdmi_pinhdmi-cec Z@hdmi-hpd dBcif-0dvp-d2d9-m0 ZZZZZ Z Z ZZZZZcif-1dvp-d2d9-m1 ZZZZZZZZZZZZephyeth-phy-int-pin dReth-phy-reset-pin dSledsled-pin Zfpmicpmic-int-l \(usb3usb30-host-drv Zjwifiwifi-en Zkchosen serial2:1500000n8adc-keys adc-keys e buttons button-recovery Recovery h 'external-gmac-clock fixed-clockgsY@ wgmac_clkinZOleds gpio-ledsfdefaultled-0  g heartbeatsdmmc-regulatorregulator-fixed hdefaulti4vcc_sdW #Kvcc-host-5v-regulatorregulator-fixed gdefaultj . 4vcc_host_5vCW #)vcc-sysregulator-fixed4vcc_sysCWiLK@LK@)vcc-wifi-regulatorregulator-fixed hdefaultk 4vcc_wifiCW # compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsvref-supplyinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpvmmc-supplycap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vnon-removablevqmmc-supplysnps,txpblclock_in_outphy-handlephy-modephy-supplysnps,aalsnps,rxpbltx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltcolorlinux,default-triggergpiovin-supplyenable-active-high