8( &firefly,roc-rk3328-ccrockchip,rk3328 +7Firefly roc-rk3328-ccaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci  cpu@1cpuarm,cortex-a53xpsci  cpu@2cpuarm,cortex-a53xpsci  cpu@3cpuarm,cortex-a53xpsci  idle-statespscicpu-sleeparm,idle-state*;Rxcsl2-cache0cacheopp-table-0operating-points-v2opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @analog-soundsimple-audio-cardi2sAnalog%okaysimple-audio-card,cpu,simple-audio-card,codec,arm-pmuarm,cortex-a53-pmu06defgA display-subsystemrockchip,display-subsystemT hdmi-soundsimple-audio-cardi2sHDMI%okaysimple-audio-card,cpu,simple-audio-card,codec,psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer06   xin24m fixed-clockZgn6wxin24mEi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s 6)7i2s_clki2s_hclk  txrx%okayi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s 6*8i2s_clki2s_hclktxrx%okayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s 6+9i2s_clki2s_hclktxrx %disabledspdif@ff030000rockchip,rk3328-spdif 6.: mclkhclk txdefault %disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep %disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd:io-domains"rockchip,rk3328-io-voltage-domain%okay,gpiorockchip,rk3328-grf-gpio9Iepower-controller!rockchip,rk3328-power-controllerU+<power-domain@6Upower-domain@5 BABUpower-domain@8FUreboot-modesyscon-reboot-modeipRB|RBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 67&baudclkapb_pclktxrxdefault  !" %disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 68'baudclkapb_pclktxrxdefault #$% %disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 69(baudclkapb_pclktxrxdefault&%okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c 6$+7 i2cpclkdefault' %disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c 6%+8 i2cpclkdefault(%okaypmic@18rockchip,rk805 )6Zwxin32krk805-clkout29Idefault*++++(hregulatorsDCDC_REG1 4vdd_logicC 4[ sregulator-state-memB@DCDC_REG24vdd_armC 4[ sregulator-state-mem~DCDC_REG34vcc_ddrsregulator-state-memDCDC_REG44vcc_ioC2Z[2Zsregulator-state-mem2ZLDO_REG14vcc_18Cw@[w@sregulator-state-memw@LDO_REG2 4vcc18_emmcCw@[w@sregulator-state-memw@LDO_REG34vdd_10CB@[B@sregulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c 6&+9 i2cpclkdefault, %disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c 6'+: i2cpclkdefault- %disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 61+ spiclkapb_pclk txrxdefault./01 %disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt 6(pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault2 %disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault3 %disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault4 %disabledpwm@ff1b0030rockchip,rk3328-pwm0 62< pwmpclkdefault5 %disableddma-controller@ff1f0000arm,pl330arm,primecell@6 apb_pclkthermal-zonessoc-thermal06tripstrip-point0@pLpassivetrip-point1@LLpassive7soc-crit@sL criticalcooling-mapsmap0W70\ ktsadc@ff250000rockchip,rk3328-tsadc% 6:x$P$tsadcapb_pclkinitdefaultsleep898B tsadc-apb:%okay6efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1aFadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( 6P %saradcapb_pclkV saradc-apb %disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500T6ZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscorefiommu@ff330200rockchip,iommu3 6` aclkiface/ %disablediommu@ff340800rockchip,iommu4@ 6bF aclkiface/ %disabledvideo-codec@ff350000rockchip,rk3328-vpu5 6 vdpuF aclkhclk<;C<iommu@ff350800rockchip,iommu5@ 6 F aclkiface/C<;video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6 6 BABaxiahbcabaccorexAB ׄׄ<=C<iommu@ff360480rockchip,iommu 6@6@ 6JB aclkiface/C<=vop@ff370000rockchip,rk3328-vop7> 6 x;aclk_vopdclk_vophclk_vop axiahbdclk<>%okayport+ endpoint@0Q?Diommu@ff373f00rockchip,iommu7? 6 ; aclkiface/%okay>hdmi@ff3c0000rockchip,rk3328-dw-hdmi<6#GFiahbisfrceca@fhdmidefault ABC:%okayports+port@0endpointQD?port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk:%okayphy@ff430000rockchip,rk3328-hdmi-phyC 6SEysysclkrefoclkrefpclk whdmi_phyZpF |cpu-version%okay@clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD:Zxx=&'(ABDC"\5H4$zEEE|n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyEphyclk wusb480m_phyZx{G%okayGotg-port$6;<=otg-bvalidotg-idlinestate%okayVhost-port 6> linestate%okayWmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ 6  =!JNbiuciuciu-driveciu-sampleр%okaydefaultHIJK '4BLNmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ 6  >"KObiuciuciu-driveciu-sampleр %disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ 6 ?#LPbiuciuciu-driveciu-sampleр%okay[hwdefault MNOBNethernet@ff540000rockchip,rk3328-gmacT 6macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth:%okayxdfPPinputQrgmiidefaultR ) 'P$ ethernet@ff550000rockchip,rk3328-gmacU: 6macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb stmmacethrmiiSoutput %disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultTUSusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X 6Motg/host7IX@ aV fusb2-phy%okayusb@ff5c0000 generic-ehci\ 6 NGaWfusb%okayusb@ff5d0000 generic-ohci] 6 NGaWfusb%okayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` 6C`aref_clksuspend_clkbus_clk/host gutmi_widep %okayinterrupt-controller@ff811000 arm,gic-400  /@ @ `  6 crypto@ff060000rockchip,rk3328-crypto@ 6PQ;hclk_masterhclk_slavesclkD crypto-rstpinctrlrockchip,rk3328-pinctrl:+ Dgpio@ff210000rockchip,gpio-bank! 639I / cgpio@ff220000rockchip,gpio-bank" 649I / )gpio@ff230000rockchip,gpio-bank# 659I / gpio@ff240000rockchip,gpio-bank$ 669I / pcfg-pull-up KZpcfg-pull-down Xbpcfg-pull-none gXpcfg-pull-none-2ma g tapcfg-pull-up-2ma K tpcfg-pull-up-4ma K t[pcfg-pull-none-4ma g t^pcfg-pull-down-4ma X tpcfg-pull-none-8ma g t\pcfg-pull-up-8ma K t]pcfg-pull-none-12ma g t _pcfg-pull-up-12ma K t `pcfg-output-high pcfg-output-low pcfg-input-high K Ypcfg-input i2c0i2c0-xfer XX'i2c1i2c1-xfer XX(i2c2i2c2-xfer  XX,i2c3i2c3-xfer XX-i2c3-pins XXhdmi_i2chdmii2c-xfer XXBpdm-0pdmm0-clk Xpdmm0-fsync Xpdmm0-sdi0 Xpdmm0-sdi1 Xpdmm0-sdi2 Xpdmm0-sdi3 Xpdmm0-clk-sleep Ypdmm0-sdi0-sleep Ypdmm0-sdi1-sleep Ypdmm0-sdi2-sleep Ypdmm0-sdi3-sleep Ypdmm0-fsync-sleep Ytsadcotp-pin  X8otp-out  X9uart0uart0-xfer  XZ uart0-cts  X!uart0-rts  X"uart0-rts-pin  Xuart1uart1-xfer XZ#uart1-cts X$uart1-rts X%uart1-rts-pin Xuart2-0uart2m0-xfer XZuart2-1uart2m1-xfer XZ&spi0-0spi0m0-clk Zspi0m0-cs0  Zspi0m0-tx  Zspi0m0-rx  Zspi0m0-cs1  Zspi0-1spi0m1-clk Zspi0m1-cs0 Zspi0m1-tx Zspi0m1-rx Zspi0m1-cs1 Zspi0-2spi0m2-clk Z.spi0m2-cs0 Z1spi0m2-tx Z/spi0m2-rx Z0i2s1i2s1-mclk Xi2s1-sclk Xi2s1-lrckrx Xi2s1-lrcktx Xi2s1-sdi Xi2s1-sdo Xi2s1-sdio1 Xi2s1-sdio2 Xi2s1-sdio3 Xi2s1-sleep YYYYYYYYYi2s2-0i2s2m0-mclk Xi2s2m0-sclk Xi2s2m0-lrckrx Xi2s2m0-lrcktx Xi2s2m0-sdi Xi2s2m0-sdo Xi2s2m0-sleep` YYYYYYi2s2-1i2s2m1-mclk Xi2s2m1-sclk Xi2sm1-lrckrx Xi2s2m1-lrcktx Xi2s2m1-sdi Xi2s2m1-sdo Xi2s2m1-sleepP YYYYYspdif-0spdifm0-tx Xspdif-1spdifm1-tx Xspdif-2spdifm2-tx Xsdmmc0-0sdmmc0m0-pwren [sdmmc0m0-pin [sdmmc0-1sdmmc0m1-pwren [sdmmc0m1-pin [dsdmmc0sdmmc0-clk \Hsdmmc0-cmd ]Isdmmc0-dectn [Jsdmmc0-wrprt [sdmmc0-bus1 ]sdmmc0-bus4@ ]]]]Ksdmmc0-pins [[[[[[[[sdmmc0extsdmmc0ext-clk ^sdmmc0ext-cmd [sdmmc0ext-wrprt [sdmmc0ext-dectn [sdmmc0ext-bus1 [sdmmc0ext-bus4@ [[[[sdmmc0ext-pins [[[[[[[[sdmmc1sdmmc1-clk  \sdmmc1-cmd  ]sdmmc1-pwren ]sdmmc1-wrprt ]sdmmc1-dectn ]sdmmc1-bus1 ]sdmmc1-bus4@ ]]]]sdmmc1-pins  [ [[[[[[[[emmcemmc-clk _Memmc-cmd `Nemmc-pwren Xemmc-rstnout Xemmc-bus1 `emmc-bus4@ ````emmc-bus8 ````````Opwm0pwm0-pin X2pwm1pwm1-pin X3pwm2pwm2-pin X4pwmirpwmir-pin X5gmac-1rgmiim1-pins`  \ ^^\^^^ ^ ^\ \^^\\\ \^\\\\Rrmiim1-pins a_aaaa a a_ _ X XXXXXgmac2phyfephyled-speed10 Xfephyled-duplex Xfephyled-rxm1 XTfephyled-txm1 Xfephyled-linkm1 XUtsadc_pintsadc-int  Xtsadc-pin  Xhdmi_pinhdmi-cec XAhdmi-hpd bCcif-0dvp-d2d9-m0 XXXXX X X XXXXXcif-1dvp-d2d9-m1 XXXXXXXXXXXXpmicpmic-int-l Z*usb2usb20-host-drv Xfchosen serial2:1500000n8external-gmac-clock fixed-clockgsY@ wgmac_clkinZPdc-12vregulator-fixed4dc_12vsC[gsdmmc-regulatorregulator-fixed cdefaultd4vcc_sdC2Z[2Z Lsdmmcio-regulatorregulator-gpio ew@2Z 4vcc_sdio voltageCw@[2Zs +vcc-host1-5v-regulatorregulator-fixed  )defaultf 4vcc_host1_5vs +vcc-sysregulator-fixed4vcc_syssCLK@[LK@ g+vcc-phy-regulatorregulator-fixed4vcc_physQleds gpio-ledsled-0 firefly:blue:power heartbeat h onled-1 firefly:yellow:user mmc1 h off compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removablesnps,txpblclock_in_outphy-supplyphy-modesnps,aalsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,rxpbltx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplygpiosregulator-typeenable-active-highlabellinux,default-triggerdefault-state