|8vD(@v &firefly,roc-rk3308-ccrockchip,rk3308 +7Firefly ROC-RK3308-CC boardaliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000/spi@ff140000/mmc@ff480000/mmc@ff490000cpus+cpu@0cpuarm,cortex-a35psciZ cpu@1cpuarm,cortex-a35psci cpu@2cpuarm,cortex-a35psci cpu@3cpuarm,cortex-a35psci idle-states(pscicpu-sleeparm,idle-state5F]xn~ l2-cachecache opp-table-0operating-points-v2 opp-408000000Q ~~r`@opp-600000000#F ~~r`@opp-8160000000, r`@opp-1008000000< **r`@arm-pmuarm,cortex-a35-pmu0STUV external-mac-clock fixed-clock mac_clkin'psci arm,psci-1.0smctimerarm,armv8-timer0   xin24m fixed-clock'n6xin24m Rgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfd Nreboot-modesyscon-reboot-mode4;RBKRBWRBcRBqRB syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfd@+usb2phy@100rockchip,rk3308-usb2phy Hphyclk usb480m_phy' disabled otg-port$CDEotg-bvalidotg-idlinestate disabled :host-port J linestate disabled ;syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default + disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default +okayrtc@51 nxp,pcf8563Q'i2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default+ disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk default+ disabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt   disabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault  disabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault  disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefaultokayserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart baudclkapb_pclkdefault  disabledspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclktxrxdefault disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclktxrxdefault !"# disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclk$$txrxdefault%&'( disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault) disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault* disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm y pwmpclkdefault+ disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm0y pwmpclkdefault, disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkdefault- disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkactive.okay `pwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm x pwmpclkdefault/ disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm0x pwmpclkdefault0 disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault1okay epwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault2 disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm  pwmpclkdefault3 disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm0 pwmpclkdefault4 disabledrktimer@ff1a0000rockchip,rk3288-timer   pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc %%saradcapb_pclk/F 6saradc-apb disableddma-controller@ff2c0000arm,pl330arm,primecell,@B apb_pclkY dma-controller@ff2d0000arm,pl330arm,primecell-@B apb_pclkY $i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s5 4\i2s_clki2s_hclk$$ txrx/6reset-mreset-hdefault5678 disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s6 5^i2s_clki2s_hclk$ rx/6reset-mreset-h disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif: 7b mclkhclk$ txdefault9 disabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2@ Botgdotgl~@ : usb2-phy disabledusb@ff440000 generic-ehciD G ;usb disabledusb@ff450000 generic-ohciE H ;usb disabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcH@ L 012biuciuciu-driveciu-sampleрdefault<=>?okay,+@7Ammc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcI@ M :;<biuciuciu-driveciu-sampleрokayDSmmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcJ@ N 567biuciuciu-driveciu-sampleрdefault BCD disablednand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfcK@ Q-ahbnfc-aрEFGHIJKdefault disabledethernet@ff4e0000rockchip,rk3308-gmacN @macirq@@BBA@C[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedvrmiidefaultLM/} 6stmmacethN disabledspi@ff4c0000 rockchip,sfcL@ R=clk_sfchclk_sfc OPQdefault disabledclock-controller@ff500000rockchip,rk3308-cruPRxin24mN'a interrupt-controller@ff580000 arm,gic-400@XX X@ X`    sram@fff80000 mmio-sram+ddr-sram@0vad-sram@8000pinctrlrockchip,rk3308-pinctrlN+defaultSgpio@ff220000rockchip,gpio-bank" ( ^gpio@ff230000rockchip,gpio-bank# )gpio@ff240000rockchip,gpio-bank$ *gpio@ff250000rockchip,gpio-bank% +gpio@ff260000rockchip,gpio-bank& , cpcfg-pull-up ]pcfg-pull-down Zpcfg-pull-none Vpcfg-pull-none-2ma pcfg-pull-up-2ma pcfg-pull-up-4ma  \pcfg-pull-none-4ma  [pcfg-pull-down-4ma pcfg-pull-none-8ma  Tpcfg-pull-up-8ma  Upcfg-pull-none-12ma  Xpcfg-pull-up-12ma  Wpcfg-pull-none-smt Ypcfg-output-high/pcfg-output-low;pcfg-input-highFpcfg-inputFemmcemmc-clkS Temmc-cmdSUemmc-pwrenS Vemmc-rstnS Vemmc-bus1SUemmc-bus4@SUUUUemmc-bus8SUUUUUUUUflashflash-csn0S V Hflash-rdyS V Jflash-aleS V Eflash-cleS V Gflash-wrnSV Kflash-rdnS V Iflash-bus8SWWWWWWWW Fsfcsfc-bus4@SVVVV Qsfc-bus2 SVVsfc-cs0SV Psfc-clkSV Ogmacrmii-pinsSXXXVVVVV V Lmac-refclk-12maS X Mmac-refclkS Vgmac-m1rmiim1-pinsSXXXVVVVV Vmacm1-refclk-12maS Xmacm1-refclkS Vi2c0i2c0-xfer SYY i2c1i2c1-xfer S Y Y i2c2i2c2-xfer SYY i2c3-m0i2c3m0-xfer SYY i2c3-m1i2c3m1-xfer S Y Yi2c3-m2i2c3m2-xfer SYYi2s_2ch_0i2s-2ch-0-mclkS Vi2s-2ch-0-sclkS V 5i2s-2ch-0-lrckSV 6i2s-2ch-0-sdoSV 8i2s-2ch-0-sdiSV 7i2s_8ch_0i2s-8ch-0-mclkSVi2s-8ch-0-sclktxSVi2s-8ch-0-sclkrxSVi2s-8ch-0-lrcktxSVi2s-8ch-0-lrckrxSVi2s-8ch-0-sdo0S Vi2s-8ch-0-sdo1S Vi2s-8ch-0-sdo2S Vi2s-8ch-0-sdo3S Vi2s-8ch-0-sdi0S Vi2s-8ch-0-sdi1SVi2s-8ch-0-sdi2SVi2s-8ch-0-sdi3SVi2s_8ch_1_m0i2s-8ch-1-m0-mclkSVi2s-8ch-1-m0-sclktxSVi2s-8ch-1-m0-sclkrxSVi2s-8ch-1-m0-lrcktxSVi2s-8ch-1-m0-lrckrxSVi2s-8ch-1-m0-sdo0SVi2s-8ch-1-m0-sdo1-sdi3SVi2s-8ch-1-m0-sdo2-sdi2S Vi2s-8ch-1-m0-sdo3_sdi1S Vi2s-8ch-1-m0-sdi0S Vi2s_8ch_1_m1i2s-8ch-1-m1-mclkS Vi2s-8ch-1-m1-sclktxS Vi2s-8ch-1-m1-sclkrxSVi2s-8ch-1-m1-lrcktxSVi2s-8ch-1-m1-lrckrxSVi2s-8ch-1-m1-sdo0SVi2s-8ch-1-m1-sdo1-sdi3SVi2s-8ch-1-m1-sdo2-sdi2SVi2s-8ch-1-m1-sdo3_sdi1SVi2s-8ch-1-m1-sdi0SVpdm_m0pdm-m0-clkSVpdm-m0-sdi0S Vpdm-m0-sdi1S Vpdm-m0-sdi2S Vpdm-m0-sdi3SVpdm_m1pdm-m1-clkSVpdm-m1-sdi0SVpdm-m1-sdi1SVpdm-m1-sdi2SVpdm-m1-sdi3SVpdm_m2pdm-m2-clkmSVpdm-m2-clkSVpdm-m2-sdi0S Vpdm-m2-sdi1SVpdm-m2-sdi2SVpdm-m2-sdi3SVpwm0pwm0-pinS Vpwm0-pin-pull-downS Z 1pwm1pwm1-pinSV 2pwm1-pin-pull-downSZpwm2pwm2-pinSV 3pwm2-pin-pull-downSZpwm3pwm3-pinSV 4pwm3-pin-pull-downSZpwm4pwm4-pinSV -pwm4-pin-pull-downSZpwm5pwm5-pinSVpwm5-pin-pull-downSZ .pwm6pwm6-pinSV /pwm6-pin-pull-downSZpwm7pwm7-pinSV 0pwm7-pin-pull-downSZpwm8pwm8-pinS V )pwm8-pin-pull-downS Zpwm9pwm9-pinS V *pwm9-pin-pull-downS Zpwm10pwm10-pinS V +pwm10-pin-pull-downS Zpwm11pwm11-pinSV ,pwm11-pin-pull-downSZrtcrtc-32kSV Ssdmmcsdmmc-clkS[ <sdmmc-cmdS\ =sdmmc-detS\ >sdmmc-pwrenS[sdmmc-bus1S\sdmmc-bus4@S\\\\ ?sdiosdio-clkST Dsdio-cmdSU Csdio-pwrenSTsdio-wrptSTsdio-intnSTsdio-bus1SUsdio-bus4@SUUUU Bspdif_inspdif-inSVspdif_outspdif-outSV 9spi0spi0-clkS\ spi0-csn0S\ spi0-misoS\ spi0-mosiS\ spi1spi1-clkS \ spi1-csn0S \ !spi1-misoS \ "spi1-mosiS \ #spi1-m1spi1m1-misoS\spi1m1-mosiS\spi1m1-clkS\spi1m1-csn0S \spi2spi2-clkS\ %spi2-csn0S\ &spi2-misoS\ 'spi2-mosiS\ (tsadctsadc-otp-pinS Vtsadc-otp-outS Vuart0uart0-xfer S]] uart0-ctsSV uart0-rtsSV uart0-rts-pinSVuart1uart1-xfer S]] uart1-ctsSV uart1-rtsSV uart2-m0uart2m0-xfer S]] uart2-m1uart2m1-xfer S]]uart3uart3-xfer S ] ] uart3-m1uart3m1-xfer S]]uart4uart4-xfer S ]] uart4-ctsSV uart4-rtsSV uart4-rts-pinSVir-receiverir-recv-pinSV _buttonspwr-keyS]chosenaserial2:1500000n8ir-receivergpio-ir-receiver m^default_ir_tx pwm-ir-txs`aleds gpio-ledsled-0xfirefly:red:power~ir-power-clickon m^led-1xfirefly:blue:user~ir-user-clickoff m^ typec-vcc5vregulator-fixed typec_vcc5vLK@LK@ avcc5v0-sysregulator-fixed vcc5v0_sysLK@LK@a bvcc-ioregulator-fixedvcc_io2Z2Zb dvcc-sdmmcregulator-gpio vcc_sdmmcw@2Z m^w@2Zb Avcc-sdregulator-fixed cvcc_sd2Z2Zd @vdd-corepwm-regulatorse vdd_core xr`5b vdd-logregulator-fixedvdd_logb compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesstatusinterrupt-names#phy-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesarm,pl330-periph-burst#dma-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removableassigned-clock-ratesphy-moderockchip,grf#reset-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathgpiospwmslabellinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioregulator-settling-time-up-uspwm-supply