8(BP 3,Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2$2qcom,ipq5018-rdp432-c2qcom,ipq5018clockssleep-clk 2fixed-clock=J}Zxo-board-clk 2fixed-clock=Jn6Zcpus cpu@0bcpu2arm,cortex-a53nrpscicpu@1bcpu2arm,cortex-a53nrpscil2-cache2cacheZfirmwarescm2qcom,scm-ipq5018qcom,scmmemory@40000000bmemoryn@pmu2arm,cortex-a53-pmu psci 2arm,psci-1.0ysmcreserved-memory tz@4ac00000nJ soc@0 2simple-bus pinctrl@10000002qcom,ipq5018-tlmmn0 / Zuart1-stategpio31gpio32gpio33gpio34 "blsp1_uart1+:Zsdc-default-stateZclk-pinsgpio9 "sdc1_clk+Icmd-pinsgpio8 "sdc1_cmd+Vdata-pinsgpio4gpio5gpio6gpio7 "sdc1_data+Iclock-controller@18000002qcom,gcc-ipq5018n$c=jwZmmc@7804000%2qcom,ipq5018-sdhciqcom,sdhci-msm-v5n@hc{hc_irqpwr_irqcYZifacecorexookaydefault qserial@78af000%2qcom,msm-uartdm-v1.4qcom,msm-uartdmn kc coreifaceokaydefaultinterrupt-controller@b0000002qcom,msm-qgic2 n   @      Zv2m@02arm,gic-v2m-framenv2m@10002arm,gic-v2m-framentimer@b1200002arm,armv7-timer-memn  frame@b120000n   !frame@b123000n 0 ! disabledframe@b124000! n @ disabledframe@b125000n P ! disabledframe@b126000n ` ! disabledframe@b127000n p ! disabledframe@b128000n  ! disabledtimer2arm,armv8-timer0aliases./soc@0/serial@78af000chosen6serial0:115200n8 interrupt-parent#address-cells#size-cellsmodelcompatible#clock-cellsclock-frequencyphandledevice_typeregenable-methodnext-level-cachecache-levelcache-sizecache-unifiedinterruptsrangesno-mapgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspinsfunctiondrive-strengthbias-pull-downbias-disablebias-pull-upclocks#reset-cells#power-domain-cellsreg-namesinterrupt-namesclock-namesnon-removablestatuspinctrl-0pinctrl-namesmmc-ddr-1_8vmmc-hs200-1_8vmax-frequencybus-widthmsi-controllerframe-numberserial0stdout-path