8|(D$mediatek,mt8186-evbmediatek,mt8186 +!7MediaTek MT8186 evaluation board =embeddedaliasesJ/soc/ovl@14005000O/soc/ovl@14006000W/soc/rdma@14007000]/soc/rdma@1401f000c/soc/serial@11002000ccimediatek,mt8186-ccikrcciintermediate~!opp-table-ccioperating-points-v2opp-500000000e 'opp-560000000!` Lopp-612000000$za opp-682000000(~ opp-752000000,Ҝ YF opp-8220000000  opp-8750000004'p  opp-9270000007@ 5 opp-980000000:i ~> opp-1050000000> opp-1120000000B )$opp-1155000000D opp-1190000000F opp-1260000000K~opp-1330000000OF0)opp-1400000000SrNRopp-table-cluster0operating-points-v2opp-500000000e 'opp-774000000."M Lopp-8750000004'p `opp-975000000:Q opp-1075000000@2 q opp-1175000000F  X opp-1275000000K 5 opp-1375000000Q  opp-1500000000Yh/  opp-1618000000`p Yopp-1666000000cM$ opp-1733000000gK{@Hopp-1800000000kI~opp-1866000000o8opp-1933000000s7=@Zopp-2000000000w5Ropp-table-cluster1operating-points-v2"opp-774000000."M Lopp-8350000001 opp-9190000006 opp-1002000000;N YFopp-1085000000@@ X opp-1169000000E@ 5 opp-1308000000M  opp-1419000000T8 Y opp-1530000000[1 t opp-1670000000c-Zopp-1733000000gK{@opp-1796000000k sopp-1860000000nYԼopp-1923000000r6dopp-1986000000v_vopp-2050000000z0cpus+cpu-mapcluster0core0core1core2core3core4core5core6core7cpu@0cpuarm,cortex-a55psciw5krcpuintermediate~T~'7D@Vcp@ !cpu@100cpuarm,cortex-a55psciw5krcpuintermediate~T~'7D@Vcp@ !cpu@200cpuarm,cortex-a55psciw5krcpuintermediate~T~'7D@Vcp@ !cpu@300cpuarm,cortex-a55psciw5krcpuintermediate~T~'7D@Vcp@ !cpu@400cpuarm,cortex-a55psciw5krcpuintermediate~T~'7D@Vcp@ !cpu@500cpuarm,cortex-a55psciw5krcpuintermediate~T~'7D@Vcp@ !cpu@600cpuarm,cortex-a76psciz0krcpuintermediate~"O'#$7D@Vcp@%!cpu@700cpuarm,cortex-a76psciz0krcpuintermediate~"O'#$7D@Vcp@%!idle-statespscicpu-retention-larm,idle-state2d@cpu-retention-barm,idle-state2dx#cpu-off-larm,idle-stated4cpu-off-barm,idle-statedl$l2-cache0cache#9F@X&/ l2-cache1cache#9F@X&/%l3-cachecache#9F@X/&fixed-factor-clock-13mfixed-factor-clock=k'JT_clk13m4oscillator-26m fixed-clock=_clk26m'oscillator-32k fixed-clock=_clk32kopp-table-gpuoperating-points-v2Jopp-299000000` Xropp-332000000 hropp-366000000з <ropp-400000000ׄ Ҧropp-434000000P zropp-484000000A 4Nropp-535000000s }ropp-586000000" `ropp-637000000%@ 4ropp-690000000)  @ropp-743000000,IG ropp-796000000/q ropp-8500000002 5ropp-900000000-35 Propp-900000000-45 |ropp-900000000-55 r0opp-950000000-38ـ ropp-950000000-48ـ Yropp-950000000-58ـ Pr0opp-1000000000-3;~ropp-1000000000-4; tropp-1000000000-5; Yr0pmu-a55arm,cortex-a55-pmu (pmu-a76arm,cortex-a76-pmu )psci arm,psci-1.0smctimerarm,armv8-timer @   soc+ simple-businterrupt-controller@c000000 arm,gic-v3     ppi-partitionsinterrupt-partition-0(interrupt-partition-1)syscon@c53a000mediatek,mt8186-mcusyssyscon S=syscon@10000000 mediatek,mt8186-topckgensyscon=+syscon@10001000#mediatek,mt8186-infracfg_aosyscon=,syscon@10003000mediatek,mt8186-pericfgsyscon0Epinctrl@10005000mediatek,mt8186-pinctrlP "$&*,Biocfg0iocfg_ltiocfg_lmiocfg_lbiocfg_bliocfg_rbiocfg_rteint**i2c0-default-pins9pins-bus%2Ji2c1-default-pins:pins-bus%2Ji2c2-default-pins;pins-bus%2Ji2c3-default-pins<pins-bus%2Ji2c4-default-pins=pins-bus%2Ji2c5-default-pins>pins-bus%2Ji2c6-default-pins?pins-busW2Ji2c7-default-pins@pins-bus%2Ji2c8-default-pinsApins-bus%2Ji2c9-default-pinsBpins-busW2Jsyscon@10006000)mediatek,mt8186-scpsyssysconsimple-mfd`power-controller!mediatek,mt8186-power-controller+d7power-domain@0k+rmfg00+dpower-domain@1x,+dpower-domain@2dpower-domain@3dpower-domain@17k++$rsubsys-csirx-top0subsys-csirx-top1dpower-domain@4k+,=rsys_ckref_ckdpower-domain@5k,B,?rsys_ckref_ckdpower-domain@18k+/+>raudioadspsubsys-adsp-bus+dpower-domain@19+dpower-domain@20x,dpower-domain@16x,dpower-domain@60k+*++- ---Mrdispmdpsubsys-smi-infrasubsys-smi-commonsubsys-smi-galssubsys-smi-iommux,+dpower-domain@14k+). rvdec0larbx,dpower-domain@10 8k++++ /+#+%6rcam0cam1cam2cam3galssubsys-cam-tmsubsys-cam-topx,+dpower-domain@12 dpower-domain@11 dpower-domain@7k0+&rgalssubsys-img-topx,+dpower-domain@8dpower-domain@9 (k+'1111Prsubsys-ipe-topsubsys-ipe-larb0subsys-ipe-larb1subsys-ipe-smisubsys-ipe-galsx,dpower-domain@13 k+$2rvenc0subsys-larbx,dpower-domain@15k+:33%rwpe0subsys-larb-cksubsys-larb-pclkx,dwatchdog@10007000mediatek,mt8186-wdtpCsyscon@1000c000"mediatek,mt8186-apmixedsyssyscon=pwrap@1000d000mediatek,mt8186-pwrapsysconpwrapk,, rspiwrapspmi@10015000*mediatek,mt8186-spmimediatek,mt8195-spmi P pmifspmimstk,,+2(rpmif_sys_ckpmif_tmr_ckspmimst_clk_mux+2+t  disabledtimer@10017000,mediatek,mt8186-timermediatek,mt6765-timerpk4mailbox@1022c000mediatek,mt8186-gce"@k,rgceKscp@10500000mediatek,mt8186-scp P\ sramcfgadsp@10680000mediatek,mt8186-dsp@h hhcfgsramsecbusk+/+>raudiodspadsp_bus+/+> '+Erxtx567 disabledmailbox@10686100mediatek,mt8186-adsp-mboxhai5mailbox@10687100mediatek,mt8186-adsp-mboxhqj6spi@11000000mediatek,mt8186-nor k+3,O,c,drspisfaxiaxi_s+3+X% disabledadc@11001000.mediatek,mt8186-auxadcmediatek,mt8173-auxadck,"rmainserial@11002000*mediatek,mt8186-uartmediatek,mt6577-uart p k', rbaudbusokayserial@11003000*mediatek,mt8186-uartmediatek,mt6577-uart0q k', rbaudbus disabledi2c@11007000mediatek,mt8186-i2c p ik8,' rmaindmaJ+okaydefault9i2c@11008000mediatek,mt8186-i2c  jk8,' rmaindmaJ+okay&@default:i2c@11009000mediatek,mt8186-i2c  kk8,' rmaindmaJ+okay&'default;i2c@1100f000mediatek,mt8186-i2c  lk8,' rmaindmaJ+okaydefault<i2c@11011000mediatek,mt8186-i2c  mk8,' rmaindmaJ+okaydefault=i2c@11016000mediatek,mt8186-i2c ` bk8,' rmaindmaJ+okaydefault>i2c@1100d000mediatek,mt8186-i2c  ck8,' rmaindmaJ+okaydefault?i2c@11004000mediatek,mt8186-i2c @ nk8,' rmaindmaJ+okaydefault@i2c@11005000mediatek,mt8186-i2c P ok8,' rmaindmaJ+okaydefaultAspi@1100a000(mediatek,mt8186-spimediatek,mt6765-spi+k+K+ ,rparent-clksel-clkspi-clk disabledpwm@1100e0002mediatek,mt8186-disp-pwmmediatek,mt8183-disp-pwm@k+,4rmainmm disabledspi@11010000(mediatek,mt8186-spimediatek,mt6765-spi+k+K+ ,8rparent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8186-spimediatek,mt6765-spi+ k+K+ ,;rparent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8186-spimediatek,mt6765-spi+0k+K+ ,<rparent-clksel-clkspi-clk disabledspi@11014000(mediatek,mt8186-spimediatek,mt6765-spi+@tk+K+ ,Jrparent-clksel-clkspi-clk disabledspi@11015000(mediatek,mt8186-spimediatek,mt6765-spi+Puk+K+ ,Krparent-clksel-clkspi-clk disabledclock-controller@11017000mediatek,mt8186-imp_iic_wrapp=8serial@11018000*mediatek,mt8186-uartmediatek,mt6577-uart k', rbaudbus disabledi2c@11019000mediatek,mt8186-i2c  dk8 ,' rmaindmaJ+okaydefaultBaudio-controller@11210000mediatek,mt8186-sound! k,,,6+++F+ + ++e++h+?+@+A+B+C++++++,'}raud_infra_clkmtkaif_26m_clktop_mux_audiotop_mux_audio_inttop_mainpll_d2_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d8top_mux_aud_eng2top_apll2_d8top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s4_m_seltop_tdm_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div4top_apll12_div_tdmtop_mux_audio_htop_clk26m_clkKx,_+qC xaudiosys disabledusb@11201000#mediatek,mt8186-mtu3mediatek,mtu3  - > macippc(k+,=,3,,>$rsys_ckref_ckmcu_ckdma_ckxhci_ck/D7+ disabledusb@11200000'mediatek,mt8186-xhcimediatek,mtk-xhci mac(k+,=,3,,>$rsys_ckref_ckmcu_ckdma_ckxhci_ck& E  disabledmmc@11230000(mediatek,mt8186-mmcmediatek,mt8183-mmc # k+ ,,U,rsourcehclksource_cgcryptod+  disabledmmc@11240000(mediatek,mt8186-mmcmediatek,mt8183-mmc $k+,,Vrsourcehclksource_cge++o disabledusb@11281000#mediatek,mt8186-mtu3mediatek,mtu3 (-(> macippc$k,B,?,7',@$rsys_ckref_ckmcu_ckdma_ckxhci_ckKFG7+ disabledusb@11280000'mediatek,mt8186-xhcimediatek,mtk-xhci(mac$k,B,?,7',@$rsys_ckref_ckmcu_ckdma_ckxhci_ckD E$ disabledt-phy@11c80000.mediatek,mt8186-tphymediatek,generic-tphy-v2+okayusb-phy@0k'rrefFusb-phy@700 k'rrefGt-phy@11ca0000.mediatek,mt8186-tphymediatek,generic-tphy-v2+okayusb-phy@0k'rrefDefuse@11cb0000%mediatek,mt8186-efusemediatek,efuse+gpu-speedbin@59cIdsi-phy@11cc0000mediatek,mt8183-mipi-txk'= _mipi_tx0_pll disabledNclock-controller@13000000mediatek,mt8186-mfgsys=Hgpu@13040000&mediatek,mt8186-maliarm,mali-bifrost@kH0 jobmmugpu77 core0core1I speed-bin~JO disabledsyscon@14000000mediatek,mt8186-mmsyssyscon=KKK-mutex@14001000mediatek,mt8186-disp-mutexk-'K&7smi@14002000mediatek,mt8186-smi-common  k----rapbsmigals0gals17Lsmi@14003000mediatek,mt8186-smi-larb0k--rapbsmi:KL7Osmi@14004000mediatek,mt8186-smi-larb@k--rapbsmi:KL7Povl@140050002mediatek,mt8186-disp-ovlmediatek,mt8192-disp-ovlPk-)XMKP7ovl@140060008mediatek,mt8186-disp-ovl-2lmediatek,mt8192-disp-ovl-2l`k-*XM!K`7rdma@140070004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdmapk-+XM"Kp7color@140090006mediatek,mt8186-disp-colormediatek,mt8173-disp-colork- -K7dpi@1400a000mediatek,mt8186-dpik+;- rpixelenginepll+;+j5 disabledportendpointccorr@1400b0006mediatek,mt8186-disp-ccorrmediatek,mt8192-disp-ccorrk-.K7aal@1400c0002mediatek,mt8186-disp-aalmediatek,mt8183-disp-aalk-0K7gamma@1400d0006mediatek,mt8186-disp-gammamediatek,mt8183-disp-gammak- 1K7postmask@1400e000<mediatek,mt8186-disp-postmaskmediatek,mt8192-disp-postmaskk- 2K7dither@1400f0008mediatek,mt8186-disp-dithermediatek,mt8183-disp-ditherk-3K7dsi@14013000mediatek,mt8186-dsi0k--Nrenginedigitalhs77q-N_dphy disabledportendpointiommu@14016000mediatek,mt8186-iommu-mm`k-rbclk98iOPQRSTUVWXYZ[\7xMrdma@1401f0004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdmak-4XM K7clock-controller@14020000mediatek,mt8186-wpesys=3smi@14023000mediatek,mt8186-smi-larb0k33rapbsmi:KL7Tclock-controller@15020000mediatek,mt8186-imgsys1=0smi@1502e000mediatek,mt8186-smi-larbk00rapbsmi: KL7Uclock-controller@15820000mediatek,mt8186-imgsys2=]smi@1582e000mediatek,mt8186-smi-larbk0]rapbsmi: KL7Vsmi@1602e000mediatek,mt8186-smi-larbk..rapbsmi:KL7Rclock-controller@1602f000mediatek,mt8186-vdecsys=.clock-controller@17000000mediatek,mt8186-vencsys=2smi@17010000mediatek,mt8186-smi-larbk22rapbsmi:KL7 Sclock-controller@1a000000mediatek,mt8186-camsys=/smi@1a001000mediatek,mt8186-smi-larbk//rapbsmi: KL7 Wsmi@1a002000mediatek,mt8186-smi-larb k//rapbsmi:KL7 Xsmi@1a00f000mediatek,mt8186-smi-larbk/^rapbsmi:KL7 Ysmi@1a010000mediatek,mt8186-smi-larbk/_rapbsmi:KL7 Zclock-controller@1a04f000mediatek,mt8186-camsys_rawa=^clock-controller@1a06f000mediatek,mt8186-camsys_rawb=_clock-controller@1b000000mediatek,mt8186-mdpsys=`smi@1b002000mediatek,mt8186-smi-larb k``rapbsmi:KL7Qclock-controller@1c000000mediatek,mt8186-ipesys=1smi@1c00f000mediatek,mt8186-smi-larbk11rapbsmi:KL7 \smi@1c10f000mediatek,mt8186-smi-larbk11rapbsmi:KL7 [chosenserial0:921600n8memory@40000000memory@ compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeovl0ovl-2l0rdma0rdma1serial0clocksclock-namesoperating-points-v2phandleopp-sharedopp-hzopp-microvoltrequired-oppscpudevice_typeregenable-methodclock-frequencydynamic-power-coefficientcapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,ccientry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-divclock-multclock-output-namesopp-supported-hwinterruptsdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-disabledrive-strength-microampinput-enablebias-pull-up#power-domain-cellsmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsstatus#mbox-cellsmbox-namesmboxespower-domains#io-channel-cellspinctrl-namespinctrl-0i2c-scl-internal-delay-ns#pwm-cellsmediatek,apmixedsysmediatek,topckgenresetsreset-namesphysmediatek,syscon-wakeupwakeup-source#phy-cellsmediatek,discthbitsinterrupt-namespower-domain-namesnvmem-cellsnvmem-cell-namesmediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusphy-namesmediatek,larbs#iommu-cellsstdout-path