8((mediatek,mt8183-pumpkinmediatek,mt8183 +7Pumpkin MT8183aliases=/soc/i2c@11007000B/soc/i2c@11011000G/soc/i2c@11009000L/soc/i2c@1100f000Q/soc/i2c@11008000V/soc/i2c@11016000[/soc/i2c@11005000`/soc/i2c@1101a000e/soc/i2c@1101b000j/soc/i2c@11014000o/soc/i2c@11015000u/soc/i2c@11017000{/soc/ovl@14008000/soc/ovl@14009000/soc/ovl@1400a000/soc/rdma@1400b000/soc/rdma@1400c000/soc/serial@11002000opp-table-cluster0operating-points-v2opp0-793000000/D8@ opp0-9100000006= }opp0-1014000000opp0-1417000000Tu@ Popp0-1508000000YA A opp0-1586000000^p 6 opp0-1625000000`ۈ@  opp0-1677000000c@5 opp0-1716000000fHf opp0-1781000000j'@opp0-1846000000nB@opp0-1924000000ropp0-1989000000v@opp-table-cluster1operating-points-v2$opp1-793000000/D8@ `opp1-9100000006= opp1-1014000000opp-689000000)N@ Popp-767000000-} A opp-8450000002]@ 6 opp-8710000003g  opp-92300000075 opp-9620000009Vf opp-1027000000=6opp-1092000000AB@opp-1144000000D0opp-1196000000GIccimediatek,mt8183-ccicciintermediate!cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3cpu@0cpuarm,cortex-a53psci#6cpuintermediateFT`m@@ !"cpu@1cpuarm,cortex-a53psci#6cpuintermediateFT`m@@ !"cpu@2cpuarm,cortex-a53psci#6cpuintermediateFT`m@@ !"cpu@3cpuarm,cortex-a53psci#6cpuintermediateFT`m@@ !"cpu@100cpuarm,cortex-a73psci#6#cpuintermediate$F`m@@%!&cpu@101cpuarm,cortex-a73psci#6#cpuintermediate$F`m@@%!&cpu@102cpuarm,cortex-a73psci#6#cpuintermediate$F`m@@%!&cpu@103cpuarm,cortex-a73psci#6#cpuintermediate$F`m@@%!&idle-statespscicpu-sleeparm,idle-state&7G cluster-sleep-0arm,idle-state&7Gcluster-sleep-1arm,idle-state&7G#l2-cache0cacheXbo@d l2-cache1cacheXbo@d%opp-table-0operating-points-v2Yopp-300000000 hopp-320000000 opp-340000000C <opp-360000000u* Ҧopp-380000000W opp-400000000ׄ zopp-420000000 opp-460000000k  Lopp-500000000e }opp-540000000 / `opp-580000000" 4opp-620000000$s opp-653000000&@ YFopp-698000000) opp-743000000,IG opp-800000000/ pmu-a53arm,cortex-a53-pmu 'r(pmu-a73arm,cortex-a73-pmu 'r)psci arm,psci-1.0smcfixed-factor-clock-13mfixed-factor-clock}*clk13m6oscillator fixed-clock}clk26m*timerarm,armv8-timer '@r   soc+ simple-busefuse@8000000%mediatek,mt8183-efusemediatek,efuse+ disabledinterrupt-controller@c000000 arm,gic-v3 'P   @ A B r 'ppi-partitionsinterrupt-partition-0(interrupt-partition-1)syscon@c530000mediatek,mt8183-mcucfgsyscon S}interrupt-controller@c530a80.mediatek,mt8183-sysirqmediatek,mt6577-sysirq ' S Pcpu-debug@d410000&arm,coresight-cpu-debugarm,primecell A+. apb_pclkcpu-debug@d510000&arm,coresight-cpu-debugarm,primecell Q+. apb_pclkcpu-debug@d610000&arm,coresight-cpu-debugarm,primecell a+. apb_pclkcpu-debug@d710000&arm,coresight-cpu-debugarm,primecell q+. apb_pclkcpu-debug@d810000&arm,coresight-cpu-debugarm,primecell +. apb_pclkcpu-debug@d910000&arm,coresight-cpu-debugarm,primecell +. apb_pclkcpu-debug@da10000&arm,coresight-cpu-debugarm,primecell +. apb_pclkcpu-debug@db10000&arm,coresight-cpu-debugarm,primecell +. apb_pclksyscon@10000000 mediatek,mt8183-topckgensyscon}syscon@10001000 mediatek,mt8183-infracfgsyscon}+syscon@10003000mediatek,mt8183-pericfgsyscon0}Lpinctrl@10005000mediatek,mt8183-pinctrlPD iocfg0iocfg1iocfg2iocfg3iocfg4iocfg5iocfg6iocfg7iocfg8eint&2, r,i2c0?pins_i2c>RSEZi2c1Hpins_i2c>QTEZi2c2Apins_i2c>ghEZi2c3Gpins_i2c>23EZi2c4@pins_i2c>ijEZi2c5Ipins_i2c>01EZi2c6>pins_cmd_dat>qrEkeyboard4pins_keyboard >[\]mmc0-pins-defaultOpins_cmd_dat$>{}~zvEpins_clk>| pins_rst>mmc0-pins-uhsPpins_cmd_dat$>{}~zvEpins_clk>| pins_ds> pins_rst>Emmc1-pins-defaultSpins_cmd_dat> "!vE pins_clk>v pins_pmu>mmc1-pins-uhsTpins_cmd_dat> "!vE pins_clk> vsyscon@10006000)mediatek,mt8183-scpsyssysconsimple-mfd`power-controller!mediatek,mt8183-power-controller+Fpower-domain@0 +/+7audioaudio1audio2power-domain@1+power-domain@2mfg+power-domain@3+-power-domain@4power-domain@5power-domain@6+power-domain@7X.......... 5mmmm-0mm-1mm-2mm-3mm-4mm-5mm-6mm-7mm-8mm-9+/+power-domain@8@00 00000.camcam-0cam-1cam-2cam-3cam-4cam-5cam-6+/power-domain@9 "1 1ispisp-0isp-1+/power-domain@10 /power-domain@11 /power-domain@12 @&#222222-vpuvpu1vpu-0vpu-1vpu-2vpu-3vpu-4vpu-5+/+power-domain@13 $vpu2+power-domain@14%vpu3+watchdog@10007000mediatek,mt8183-wdtpMsyscon@1000c000"mediatek,mt8183-apmixedsyssyscon}Epwrap@1000d000mediatek,mt8183-pwrap pwrap r)+ spiwrappmicmediatek,mt6358 ,rmt6358codecmediatek,mt6358-soundmt6358regulatormediatek,mt6358-regulatorbuck_vdram1 vdram1 0LH0]ybuck_vcore vcore 0Hj]ybuck_vpa vpa 07HP]buck_vproc11 vproc11 0Hj]y&buck_vproc12 vproc12 0Hj]y"buck_vgpu vgpu h0 Hj]3-buck_vs2 vs2 0LH0]ybuck_vmodem vmodem 0Hj]ybuck_vs1 vs1B@0'{lH0]yldo_vdram2 vdram2 '0w@] ldo_vsim1 vsim10/M`]ldo_vibr vibrO02Z]<ldo_vrf12regulator-fixed vrf12O0O]xldo_vio18regulator-fixed vio18w@0w@] yRldo_vusb vusb-0/M`]yldo_vcamioregulator-fixed vcamiow@0w@]Eldo_vcamd vcamd 0w@]Eldo_vcn18regulator-fixed vcn18w@0w@]ldo_vfe28regulator-fixed vfe28*0*]ldo_vsram_proc11  vsram_proc11 0Hj]yldo_vcn28regulator-fixed vcn28*0*]ldo_vsram_others  vsram_others 0Hj]yldo_vsram_gpu  vsram_gpu P0B@Hj]-3ldo_vxo22regulator-fixed vxo22!0!]xyldo_vefuse vefuse0]ldo_vaux18regulator-fixed vaux18w@0w@]ldo_vmch vmch,@ 02Z]<Uldo_vbif28regulator-fixed vbif28*0*]ldo_vsram_proc12  vsram_proc12 0Hj]yldo_vcama1 vcama1w@0-]Eldo_vemc vemc,@ 02Z]<Qldo_vio28regulator-fixed vio28*0*]ldo_va12regulator-fixed va12O0O]yldo_vrf18regulator-fixed vrf18w@0w@]xldo_vcn33_bt  vcn33_bt2Z05g]ldo_vcn33_wifi  vcn33_wifi2Z05g]ldo_vcama2 vcama2w@0-]Eldo_vmc vmcw@02Z]<Vldo_vldo28 vldo28*0-]ldo_vaud28regulator-fixed vaud28*0*]ldo_vsim2 vsim20/M`]rtcmediatek,mt6358-rtckeysmediatek,mt6358-keyspowerthomefkeyboard@10010000mediatek,mt6779-keypad r*kpdokaydefault4rs+> Pscp@10500000mediatek,mt8183-scp P\  sramcfg r+mainh5okaytimer@10017000,mediatek,mt8183-timermediatek,mt6765-timerp r6iommu@10205000mediatek,mt8183-m4u P rv789:;<=[mailbox@10238000mediatek,mt8183-gce#@ r+gceZauxadc@11001000.mediatek,mt8183-auxadcmediatek,mt8173-auxadc+#mainokayDserial@11002000*mediatek,mt8183-uartmediatek,mt6577-uart  r[ *+ baudbusokayserial@11003000*mediatek,mt8183-uartmediatek,mt6577-uart0 r\ *+ baudbus disabledserial@11004000*mediatek,mt8183-uartmediatek,mt6577-uart@ r] *+ baudbus disabledi2c@11005000mediatek,mt8183-i2c P rW+W+* maindma+okaydefault>i2c@11007000mediatek,mt8183-i2c p rQ+ +* maindma+okaydefault?i2c@11008000mediatek,mt8183-i2c  rR+ +*+G maindmaarb+okaydefault@i2c@11009000mediatek,mt8183-i2c  rS+ +*+I maindmaarb+okaydefaultAspi@1100a000mediatek,mt8183-spi+ rx6+parent-clksel-clkspi-clk disabledsvs@1100b000mediatek,mt8183-svs r+ mainBC(svs-calibration-datat-calibration-datathermal@1100b000mediatek,mt8183-thermal+ +# thermauxadc+ rLDECcalibration-data_pwm@1100e000mediatek,mt8183-disp-pwm rF+5mainmmpwm@11006000mediatek,mt8183-pwm`0++++++topmainpwm1pwm2pwm3pwm4i2c@1100f000mediatek,mt8183-i2c  rT+ +* maindma+okaydefaultGspi@11010000mediatek,mt8183-spi+ r|6+8parent-clksel-clkspi-clk disabledi2c@11011000mediatek,mt8183-i2c  rU+9+* maindma+okaydefaultHspi@11012000mediatek,mt8183-spi+  r6+;parent-clksel-clkspi-clk disabledspi@11013000mediatek,mt8183-spi+0 r6+<parent-clksel-clkspi-clk disabledi2c@11014000mediatek,mt8183-i2c @ r+H+*+G maindmaarb+ disabledi2c@11015000mediatek,mt8183-i2c P r+J+*+I maindmaarb+ disabledi2c@11016000mediatek,mt8183-i2c ` rV+D+*+E maindmaarb+okaydefaultIi2c@11017000mediatek,mt8183-i2c p r+F+*+E maindmaarb+ disabledspi@11018000mediatek,mt8183-spi+ r6+Kparent-clksel-clkspi-clk disabledspi@11019000mediatek,mt8183-spi+ r6+Lparent-clksel-clkspi-clk disabledi2c@1101a000mediatek,mt8183-i2c  rX+b+* maindma+ disabledi2c@1101b000mediatek,mt8183-i2c  rY+c+* maindma+ disabledusb@11201000#mediatek,mt8183-mtu3mediatek,mtu3  . >  macippc rH'JK+=+Zsys_ckref_ck ,L e+ disabledusb@11200000'mediatek,mt8183-xhcimediatek,mtk-xhci  mac rI+=+Zsys_ckref_ck disabledaudio-controller@11220000 mediatek,mt8183-audiosyssyscon"}Nmt8183-afe-pcmmediatek,mt8183-audio rM CaudiosysFDNNNNN NNNNN N N N NN+/+7  0HLKOtuvwxyz{|}~*waud_afe_clkaud_dac_clkaud_dac_predis_clkaud_adc_clkaud_adc_adda6_clkaud_apll22m_clkaud_apll24m_clkaud_apll1_tuner_clkaud_apll2_tuner_clkaud_i2s1_bclk_swaud_i2s2_bclk_swaud_i2s3_bclk_swaud_i2s4_bclk_swaud_tdm_clkaud_tml_clkaud_infra_clkmtkaif_26m_clktop_mux_audiotop_mux_aud_intbustop_syspll_d2_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d8top_mux_aud_eng2top_apll2_d8top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s3_m_seltop_i2s4_m_seltop_i2s5_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div3top_apll12_div4top_apll12_divbtop_clk26m_clkmmc@11230000mediatek,mt8183-mmc # rM++sourcehclksource_cgokaydefaultstate_uhsOOPYc q(QRUmmc@11240000mediatek,mt8183-mmc $ rN ++(sourcehclksource_cgokaydefaultstate_uhsSOTYc .;IVUV]dsi-phy@11e50000mediatek,mt8183-mipi-txE}s mipi_tx0_pllWcalibration-data\efuse@11f10000%mediatek,mt8183-efusemediatek,efuse+calib@180 Ccalib@190 Wcalib@580dBt-phy@11f40000.mediatek,mt8183-tphymediatek,generic-tphy-v2+okayusb-phy@0*refs~okayJusb-phy@700 *refsokayKsyscon@13000000mediatek,mt8183-mfgcfgsyscon}FXgpu@13040000'mediatek,mt8183b-maliarm,mali-bifrost@$r jobmmugpuXFFFcore0core1core2Y-syscon@14000000mediatek,mt8183-mmsyssyscon}ZZZ.dma-controller0@14001000mediatek,mt8183-mdp3-rdmaZF. .[ ZZmdp3-rsz0@14003000mediatek,mt8183-mdp3-rsz0Z0.mdp3-rsz1@14004000mediatek,mt8183-mdp3-rsz@Z@.dma-controller@14005000mediatek,mt8183-mdp3-wrotPZP!F.[mdp3-wdma@14006000mediatek,mt8183-mdp3-wdma`Z`"F.)[ovl@14008000mediatek,mt8183-disp-ovl rF.[Zovl@14009000mediatek,mt8183-disp-ovl-2l rF.[Zovl@1400a000mediatek,mt8183-disp-ovl-2l rF.[Zrdma@1400b000mediatek,mt8183-disp-rdma rF.[Zrdma@1400c000mediatek,mt8183-disp-rdma rF.[Zcolor@1400e0006mediatek,mt8183-disp-colormediatek,mt8173-disp-color rF.Zccorr@1400f000mediatek,mt8183-disp-ccorr rF.Zaal@14010000mediatek,mt8183-disp-aal rF.Zgamma@14011000mediatek,mt8183-disp-gamma rF.Zdither@14012000mediatek,mt8183-disp-dither  rF.Z dsi@14014000mediatek,mt8183-dsi@ rF.. \enginedigitalhs.'\dphy disabledmutex@14016000mediatek,mt8183-disp-mutex` rFZ`larb@14017000mediatek,mt8183-smi-larbp/..Fapbsmi7smi@14019000mediatek,mt8183-smi-common ....apbsmigals0gals1F/mdp3-ccorr@1401c000mediatek,mt8183-mdp3-ccorrZ1.+syscon@15020000mediatek,mt8183-imgsyssyscon}1larb@15021000mediatek,mt8183-smi-larb/1 1 . apbsmigalsF <larb@1502f000mediatek,mt8183-smi-larb/11.  apbsmigalsF 9syscon@16000000mediatek,mt8183-vdecsyssyscon}]larb@16010000mediatek,mt8183-smi-larb/]]apbsmiF 8syscon@17000000mediatek,mt8183-vencsyssyscon}^larb@17010000mediatek,mt8183-smi-larb/^^apbsmiF ;venc_jpg@17030000+mediatek,mt8183-jpgencmediatek,mtk-jpgenc r[[F ^jpgencsyscon@19000000 mediatek,mt8183-ipu_connsyscon}2syscon@19010000mediatek,mt8183-ipu_adlsyscon}syscon@19180000!mediatek,mt8183-ipu_core0syscon}syscon@19280000!mediatek,mt8183-ipu_core1syscon(}syscon@1a000000mediatek,mt8183-camsyssyscon}0larb@1a001000mediatek,mt8183-smi-larb/00. apbsmigalsF=larb@1a002000mediatek,mt8183-smi-larb /0 0 . apbsmigalsF:thermal-zonescpu-thermal$d:H_Xtripstrip-point0j v passivetrip-point1j8v passive`cpu-critj8v  criticalcooling-mapsmap0`0 map1`0tzts1$:H_Xtripscooling-mapstzts2$:H_Xtripscooling-mapstzts3$:H_Xtripscooling-mapstzts4$:H_Xtripscooling-mapstzts5$:H_Xtripscooling-mapstztsABB$:H_Xtripscooling-mapsmemory@40000000memory@chosenserial0:921600n8reserved-memory+scp_mem_region@50000000shared-dma-poolP5leds gpio-ledsled-redred ,offled-greengreen ,offthermistormurata,ncp03wf104w@pD compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9i2c10i2c11ovl0ovl-2l0ovl-2l1rdma0rdma1serial0opp-sharedphandleopp-hzopp-microvoltrequired-oppsclocksclock-namesoperating-points-v2cpudevice_typeregenable-methodcapacity-dmips-mhzcpu-idle-statesdynamic-power-coefficienti-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,cciproc-supplyentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterrupts#clock-cellsclock-divclock-multclock-output-namesclock-frequencyrangesstatus#interrupt-cellsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxmediatek,pull-up-advmediatek,drive-strength-advinput-enabledrive-strengthmediatek,pull-down-advoutput-high#power-domain-cellsmediatek,infracfgdomain-supplymediatek,smimediatek,dmic-moderegulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-always-onregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadlinux,keycodeswakeup-sourcepinctrl-namespinctrl-0linux,keymapkeypad,num-rowskeypad,num-columnsdebounce-delay-msmediatek,keys-per-groupmemory-regionmediatek,larbs#iommu-cells#mbox-cells#io-channel-cellsnvmem-cellsnvmem-cell-names#thermal-sensor-cellsresetsmediatek,auxadcmediatek,apmixedsyspower-domains#pwm-cellsphysmediatek,syscon-wakeupreset-namespinctrl-1bus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplyassigned-clocksassigned-clock-parentsnon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104cap-sdio-irqno-mmckeep-power-in-suspend#phy-cellsmediatek,discthinterrupt-namespower-domain-namesmali-supplymboxesmediatek,gce-client-regmediatek,gce-eventsiommus#dma-cellsmediatek,rdma-fifo-sizephy-namespolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionstdout-pathno-maplabelgpiosdefault-statepullup-uvpullup-ohmpulldown-ohmio-channels