!8(up*archermind,mt6797-x20-devmediatek,mt6797 +7Mediatek X20 Development Board =embeddedpsci arm,psci-0.2Jsmccpus+cpu@0Qcpuarm,cortex-a53]pscikcpu@1Qcpuarm,cortex-a53]pscikcpu@2Qcpuarm,cortex-a53]pscikcpu@3Qcpuarm,cortex-a53]pscikcpu@100Qcpuarm,cortex-a53]pscikcpu@101Qcpuarm,cortex-a53]pscikcpu@102Qcpuarm,cortex-a53]pscikcpu@103Qcpuarm,cortex-a53]pscikcpu@200Qcpuarm,cortex-a72]pscikcpu@201Qcpuarm,cortex-a72]pscikoscillator-26m fixed-clocko|clk26mtimerarm,armv8-timer 0   topckgen@10000000mediatek,mt6797-topckgenkoinfracfg_ao@10001000 mediatek,mt6797-infracfgsysconkopinctrl@10005000mediatek,mt6797-pinctrlPkP $(,!gpioiocfgliocfgbiocfgriocfgtuart0pins0uart1pins1i2c0pins0%&i2c1pins178i2c2 pins2`_i2c3 pins3KJi2c4 pins4i2c5 pins5i2c6pins6i2c7pins7power-controller@10006000mediatek,mt6797-scpsysk`  mfgmmvdecwatchdog@10007000(mediatek,mt6797-wdtmediatek,mt6589-wdtkpapmixed@1000c000mediatek,mt6797-apmixedsyskointpol-controller@10200620.mediatek,mt6797-sysirqmediatek,mt6577-sysirq$  k" "serial@11002000*mediatek,mt6797-uartmediatek,mt6577-uartk  [. baudbus 5disabledserial@11003000*mediatek,mt6797-uartmediatek,mt6577-uartk0 \. baudbus5okay