Ð þí ƒ8œ(çd$mediatek,mt6755-evbmediatek,mt6755 +7MediaTek MT6755 EVB =embeddedpsci arm,psci-0.2Jsmccpus+cpu@0Qcpuarm,cortex-a53]pscikcpu@1Qcpuarm,cortex-a53]pscikcpu@2Qcpuarm,cortex-a53]pscikcpu@3Qcpuarm,cortex-a53]pscikcpu@100Qcpuarm,cortex-a53]pscikcpu@101Qcpuarm,cortex-a53]pscikcpu@102Qcpuarm,cortex-a53]pscikcpu@103Qcpuarm,cortex-a53]pscikdummy26m fixed-clockoŒº€Œtimerarm,armv8-timer 0” ÿÿ ÿ ÿintpol-controller@10200620.mediatek,mt6755-sysirqmediatek,mt6577-sysirqŸ´ k  Œinterrupt-controller@10231000 arm,gic-400´ Ÿ@k## #@ #` Œserial@11002000*mediatek,mt6755-uartmediatek,mt6577-uartk  ”[ÅÌokayserial@11003000*mediatek,mt6755-uartmediatek,mt6577-uartk0 ”\Å ÌdisabledaliasesÓ/serial@11002000memory@40000000Qmemoryk@€chosenÛserial0:921600n8 compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typemethoddevice_typeenable-methodregclock-frequency#clock-cellsphandleinterruptsinterrupt-controller#interrupt-cellsclocksstatusserial0stdout-path