8( $'friendlyarm,nanopi-r2srockchip,rk3328 +7FriendlyElec NanoPi R2Saliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/usb@ff600000/device@2}/mmc@ff500000cpus+cpu@0cpuarm,cortex-a53xpsci cpu@1cpuarm,cortex-a53xpsci cpu@2cpuarm,cortex-a53xpsci cpu@3cpuarm,cortex-a53xpsci idle-statespscicpu-sleeparm,idle-state%6Mx^nl2-cache0cacheopp_table0operating-points-v2opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @analog-soundsimple-audio-cardi2sAnalog disabledsimple-audio-card,cpu simple-audio-card,codec arm-pmuarm,cortex-a53-pmu0defg" display-subsystemrockchip,display-subsystem5  disabledhdmi-soundsimple-audio-cardi2sHDMI disabledsimple-audio-card,cpu simple-audio-card,codec psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clock;Hn6Xxin24mDi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7ki2s_clki2s_hclkw  |txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8ki2s_clki2s_hclkw|txrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9ki2s_clki2s_hclkw|txrx disabledspdif@ff030000rockchip,rk3328-spdif .: kmclkhclkw |txdefault disabledpdm@ff040000 rockchip,pdm=Rkpdm_clkpdm_hclkw|rxdefaultsleep disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd:io-domains"rockchip,rk3328-io-voltage-domainokay gpiorockchip,rk3328-grf-gpio*power-controller!rockchip,rk3328-power-controller6+<power-domain@66power-domain@56power-domain@8F6reboot-modesyscon-reboot-modeJQRB]RBkRB {RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&kbaudclkapb_pclkw|txrxdefault  !" disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'kbaudclkapb_pclkw|txrxdefault #$% disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(kbaudclkapb_pclkw|txrxdefault&okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 ki2cpclkdefault' disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 ki2cpclkdefault(okaypmic@18rockchip,rk805 );Xxin32krk805-clkout2**default++++ +regulatorsDCDC_REG1vdd_log$8J 4b z0regulator-state-memB@DCDC_REG2vdd_arm$8J 4b z0regulator-state-mem~DCDC_REG3vcc_ddr$8regulator-state-memDCDC_REG4 vcc_io_33$8J2Zb2Zregulator-state-mem2ZLDO_REG1vcc_18$8Jw@bw@regulator-state-memw@LDO_REG2 vcc18_emmc$8Jw@bw@regulator-state-memw@LDO_REG3vdd_10$8JB@bB@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 ki2cpclkdefault, disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: ki2cpclkdefault- disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ kspiclkapb_pclkw |txrxdefault./01 disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< kpwmpclkdefault2 disabledpwm@ff1b0010rockchip,rk3328-pwm< kpwmpclkdefault3 disabledpwm@ff1b0020rockchip,rk3328-pwm < kpwmpclkdefault4okaypwm@ff1b0030rockchip,rk3328-pwm0 2< kpwmpclkdefault5 disableddmac@ff1f0000arm,pl330arm,primecell@ kapb_pclkthermal-zonessoc-thermal&6tripstrip-point06pBpassivetrip-point16LBpassive7soc-crit6sB criticalcooling-mapsmap0M70R atsadc@ff250000rockchip,rk3328-tsadc% :n$~P$ktsadcapb_pclkinitdefaultsleep898B tsadc-apb:okay6efuse@ff260000rockchip,rk3328-efuse&P+> kpclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1a0Eadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P5%ksaradcapb_pclkV saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"Ggpgpmmupppp0ppmmu0pp1ppmmu1 kbuscorefiommu@ff330200rockchip,iommu3 ` Gh265e_mmu kaclkifaceW disablediommu@ff340800rockchip,iommu4@ b Gvepu_mmuF kaclkifaceW disabledvideo-codec@ff350000rockchip,rk3328-vpu5  GvdpuF kaclkhclkd;k<iommu@ff350800rockchip,iommu5@  Gvpu_mmuF kaclkifaceWk<;iommu@ff360480rockchip,iommu 6@6@ J Grkvdec_mmuB kaclkifaceW disabledvop@ff370000rockchip,rk3328-vop7>  x;kaclk_vopdclk_vophclk_vop axiahbdclkd= disabledport+ endpoint@0y>Ciommu@ff373f00rockchip,iommu7?  Gvop_mmu; kaclkifaceW disabled=hdmi@ff3c0000rockchip,rk3328-dw-hdmi<#GFkiahbisfrcec?hdmidefault @AB: disabledportsportendpointyC>codec@ff410000rockchip,rk3328-codecA* kpclkmclk: disabledphy@ff430000rockchip,rk3328-hdmi-phyC SDyksysclkrefoclkrefpclk Xhdmi_phy;E cpu-version disabled?clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD:;nx=&'(ABDC"\5H4$zDDD|~n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyDkphyclk Xusb480m_phy;n{FokayFotg-port$;<=Gotg-bvalidotg-idlinestateokayShost-port > GlinestateokayTmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNkbiuciuciu-driveciu-sampleрokayGHIJdefault#0=JXKdmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KOkbiuciuciu-driveciu-sampleр disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPkbiuciuciu-driveciu-sampleр disabledethernet@ff540000rockchip,rk3328-gmacT Gmacirq8dWXZYMkstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth:qokayndfLL|inputMrgmiiNdefault$mdiosnps,dwmac-mdio+ethernet-phy@1Odefault'P )Methernet@ff550000rockchip,rk3328-gmacU: Gmacirq8TSSUVIkstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb stmmacethrmiiPq|output disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultQRPusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Mkotghost ,@ S usb2-phyokayusb@ff5c0000 generic-ehci\  NFTusbokayusb@ff5d0000 generic-ohci]  NFTusbokayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`akref_clksuspend_clkbus_clkhost ;utmi_wideDe}okay+device@2 usbbda,8153interrupt-controller@ff811000 arm,gic-400 @ @ `   pinctrlrockchip,rk3328-pinctrl:+ gpio0@ff210000rockchip,gpio-bank! 3* agpio1@ff220000rockchip,gpio-bank" 4* )gpio2@ff230000rockchip,gpio-bank# 5* egpio3@ff240000rockchip,gpio-bank$ 6* pcfg-pull-up Wpcfg-pull-down ,_pcfg-pull-none ;Upcfg-pull-none-2ma ; H^pcfg-pull-up-2ma  Hpcfg-pull-up-4ma  HXpcfg-pull-none-4ma ; H[pcfg-pull-down-4ma , Hpcfg-pull-none-8ma ; HYpcfg-pull-up-8ma  HZpcfg-pull-none-12ma ; H \pcfg-pull-up-12ma  H ]pcfg-output-high Wpcfg-output-low cpcfg-input-high  nVpcfg-input ni2c0i2c0-xfer {UU'i2c1i2c1-xfer {UU(i2c2i2c2-xfer { UU,i2c3i2c3-xfer {UU-i2c3-pins {UUhdmi_i2chdmii2c-xfer {UUApdm-0pdmm0-clk {Updmm0-fsync {Updmm0-sdi0 {Updmm0-sdi1 {Updmm0-sdi2 {Updmm0-sdi3 {Updmm0-clk-sleep {Vpdmm0-sdi0-sleep {Vpdmm0-sdi1-sleep {Vpdmm0-sdi2-sleep {Vpdmm0-sdi3-sleep {Vpdmm0-fsync-sleep {Vtsadcotp-pin { U8otp-out { U9uart0uart0-xfer { UW uart0-cts { U!uart0-rts { U"uart0-rts-pin { Uuart1uart1-xfer {UW#uart1-cts {U$uart1-rts {U%uart1-rts-pin {Uuart2-0uart2m0-xfer {UWuart2-1uart2m1-xfer {UW&spi0-0spi0m0-clk {Wspi0m0-cs0 { Wspi0m0-tx { Wspi0m0-rx { Wspi0m0-cs1 { Wspi0-1spi0m1-clk {Wspi0m1-cs0 {Wspi0m1-tx {Wspi0m1-rx {Wspi0m1-cs1 {Wspi0-2spi0m2-clk {W.spi0m2-cs0 {W1spi0m2-tx {W/spi0m2-rx {W0i2s1i2s1-mclk {Ui2s1-sclk {Ui2s1-lrckrx {Ui2s1-lrcktx {Ui2s1-sdi {Ui2s1-sdo {Ui2s1-sdio1 {Ui2s1-sdio2 {Ui2s1-sdio3 {Ui2s1-sleep {VVVVVVVVVi2s2-0i2s2m0-mclk {Ui2s2m0-sclk {Ui2s2m0-lrckrx {Ui2s2m0-lrcktx {Ui2s2m0-sdi {Ui2s2m0-sdo {Ui2s2m0-sleep` {VVVVVVi2s2-1i2s2m1-mclk {Ui2s2m1-sclk {Ui2sm1-lrckrx {Ui2s2m1-lrcktx {Ui2s2m1-sdi {Ui2s2m1-sdo {Ui2s2m1-sleepP {VVVVVspdif-0spdifm0-tx {Uspdif-1spdifm1-tx {Uspdif-2spdifm2-tx {Usdmmc0-0sdmmc0m0-pwren {Xsdmmc0m0-pin {Xsdmmc0-1sdmmc0m1-pwren {Xsdmmc0m1-pin {Xgsdmmc0sdmmc0-clk {YGsdmmc0-cmd {ZHsdmmc0-dectn {XIsdmmc0-wrprt {Xsdmmc0-bus1 {Zsdmmc0-bus4@ {ZZZZJsdmmc0-pins {XXXXXXXXsdmmc0extsdmmc0ext-clk {[sdmmc0ext-cmd {Xsdmmc0ext-wrprt {Xsdmmc0ext-dectn {Xsdmmc0ext-bus1 {Xsdmmc0ext-bus4@ {XXXXsdmmc0ext-pins {XXXXXXXXsdmmc1sdmmc1-clk { Ysdmmc1-cmd { Zsdmmc1-pwren {Zsdmmc1-wrprt {Zsdmmc1-dectn {Zsdmmc1-bus1 {Zsdmmc1-bus4@ {ZZZZsdmmc1-pins { X XXXXXXXXemmcemmc-clk {\emmc-cmd {]emmc-pwren {Uemmc-rstnout {Uemmc-bus1 {]emmc-bus4@ {]]]]emmc-bus8 {]]]]]]]]pwm0pwm0-pin {U2pwm1pwm1-pin {U3pwm2pwm2-pin {U4pwmirpwmir-pin {U5gmac-1rgmiim1-pins` { Y [[Y[[[ [ [Y Y[[YYY Y[YYYYNrmiim1-pins {^\^^^^ ^ ^\ \ U UUUUUgmac2phyfephyled-speed10 {Ufephyled-duplex {Ufephyled-rxm1 {UQfephyled-txm1 {Ufephyled-linkm1 {URtsadc_pintsadc-int { Utsadc-pin { Uhdmi_pinhdmi-cec {U@hdmi-hpd {_Bcif-0dvp-d2d9-m0 {UUUUU U U UUUUUcif-1dvp-d2d9-m1 {UUUUUUUUUUUUbuttonreset-button-pin {U`gmac2ioeth-phy-reset-pin {_Oledslan-led-pin {Ubsys-led-pin {Ucwan-led-pin {Udlanlan-vdd-pin {Uhpmicpmic-int-l {W*sdsdio-vcc-pin {Wfchosen serial2:1500000n8gmac-clock fixed-clockHsY@ Xgmac_clkin;Lkeys gpio-keys`defaultreset reset a  2leds gpio-leds bcddefaultled-0 e nanopi-r2s:green:lanled-1 a nanopi-r2s:red:sys onled-2 e nanopi-r2s:green:wansdmmcio-regulatorregulator-gpio  )fdefault vcc_io_sdio$Jw@b2Z  voltage w@2Z sdmmc-regulatorregulator-fixed agdefaultvcc_sd8J2Zb2Z Kvdd-5vregulator-fixedvdd_5v$8JLK@bLK@+vdd-5v-lanregulator-fixed  ehdefault vdd_5v_lan$8 + compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplysnps,txpblclock_in_outphy-handlephy-modephy-supplyrx_delaysnps,aaltx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio