q8 ( Q:engicam,px30-core-ctouch2engicam,px30-corerockchip,px30 +7Engicam PX30.Core C.TOUCH 2.0aliases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000/serial@ff178000/spi@ff1d0000/spi@ff1d8000/mmc@ff370000/mmc@ff380000/mmc@ff390000cpus+cpu@0cpuarm,cortex-a35psciZ!cpu@1cpuarm,cortex-a35psciZ!cpu@2cpuarm,cortex-a35psciZ! cpu@3cpuarm,cortex-a35psciZ! idle-states)pscicpu-sleeparm,idle-state6G^xo!cluster-sleeparm,idle-state6G^o!cpu0-opp-tableoperating-points-v2!opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem  disabledexternal-gmac-clock fixed-clock gmac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal(>L^ tripstrip-point-0npzpassivetrip-point-1nLzpassive!soc-critn8z criticalcooling-mapsmap0 map1 gpu-thermal(d>^ xin24m fixed-clockn6xin24m!_power-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+!apower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"power-domain@14I#syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+!io-domains$rockchip,px30-pmu-io-voltage-domainokay$$reboot-modesyscon-reboot-modeRBRB RBRBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart %%(baudclkapb_pclk4&&9txrxCMZdefault h'() disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  (i2s_clki2s_hclk4&&9txrxZdefaulth*+,-r disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s (i2s_clki2s_hclk4&&9txrxZdefaulth./01r disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   !syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+!4io-domains rockchip,px30-io-voltage-domainokay$$$$$2lvdsrockchip,px30-lvds3dphy 4lvds disabledports+port@0+endpoint@0)5!endpoint@1)6!serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart I(baudclkapb_pclk4&&9txrxCMZdefault h789 disabledserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart J(baudclkapb_pclk4&&9txrxCMZdefaulth:okayserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart K(baudclkapb_pclk4&&9txrxCMZdefault h;<= disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart L(baudclkapb_pclk4&& 9txrxCMZdefault h>?@ disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart M(baudclkapb_pclk4& & 9txrxCMZdefault hABC disabledi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN (i2cpclk ZdefaulthD+okaypmic@20rockchip,rk809  EZdefaulthF9Zrk808-clkout1rk808-clkout2hGtGGGHHHHGregulatorsDCDC_REG1vdd_log ~!p9qregulator-state-memNf~DCDC_REG2vdd_arm ~!p9q!regulator-state-memf~DCDC_REG3vcc_ddrregulator-state-memNDCDC_REG4vcc_3v3 2Z!2Z!$regulator-state-memNf2ZDCDC_REG5 vcc3v3_sys 2Z!2Z!Hregulator-state-memNf2ZLDO_REG1vcc_1v0 B@!B@regulator-state-memNfB@LDO_REG2vcc_1v8 w@!w@!2regulator-state-memNfw@LDO_REG3vdd_1v0 B@!B@regulator-state-memNfB@LDO_REG4 vcc3v0_pmu 2Z!2Zregulator-state-memNf2ZLDO_REG5 vccio_sd w@!2Zregulator-state-memNf2ZSWITCH_REG1 vcc3v3_lcdSWITCH_REG2 vcc5v0_hosti2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO (i2cpclk ZdefaulthI+ disabledi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP (i2cpclk  ZdefaulthJ+ disabledi2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q (i2cpclk  ZdefaulthK+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $U(spiclkapb_pclk4& & 9txrxZdefaulthLMNO+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %V(spiclkapb_pclk4&&9txrxZdefaulthPQRST+ disabledwatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ % disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthUokaypwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthV disabledpwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthW disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S (pwmpclkZdefaulthX disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthY disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthZ disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulth[ disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T (pwmpclkZdefaulth\ disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& (pclktimerdmac@ff240000arm,pl330arm,primecell$@ (apb_pclk!&tsadc@ff280000rockchip,px30-tsadc( $,P,X(tsadcapb_pclk tsadc-apb 4Zinitdefaultsleeph]^!]+okayAX! saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( Ts-W(saradcapb_pclk saradc-apb disablednvmem@ff290000rockchip,px30-otp)@/Za(otpapb_pclkphyphy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ _% (xin24mgpll 48@IFq рр !clock-controller@ff2bc000rockchip,px30-pmucru+_(xin24m 4%%% G!%syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy % (phyclk` usb480m_phyokay!`host-port D linestateokay!cotg-port$BA@otg-bvalidotg-idlinestateokay!bphy@ff2e0000rockchip,px30-dsi-dphy.% E (refpclk>apba  disabled!3usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >(otgotg@ b usb2-phyaokayusb@ff340000 generic-ehci4 <cusbaokayusb@ff350000 generic-ohci5 =cusbaokayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[(stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed 4rmiiZdefaulthdea ^ stmmacethokayoutput%$0 FPP [f mmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CD(biuciuciu-driveciu-samplekuрZdefaulthghijaokay $$mmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EF(biuciuciu-driveciu-samplekuрZdefault hklma okay+nwifi@1brcm,bcm4329-fmacmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GH(biuciuciu-driveciu-samplekuрZdefault hopqa okay&nand-controller@ff3b0000rockchip,px30-nfc;@ 97(ahbnfc7рZdefault hrstuvwxya  disabledopp-table2operating-points-v2!zopp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuIaz disabled!dsi@ff450000rockchip,px30-mipi-dsiE KD(pclk3dphya =apb 4+ disabledports+port@0+endpoint@0){!~endpoint@1)|!vop@ff460000rockchip,px30-vop-bigF M(aclk_vopdclk_vophclk_vop345 axiahbdclk5}a  disabledport+! endpoint@0)~!{endpoint@1)!5iommu@ff460f00rockchip,iommuF M (aclkifacea < disabled!}vop@ff470000rockchip,px30-vop-litG N(aclk_vopdclk_vophclk_vop789 axiahbdclk5a  disabledport+! endpoint@0)!|endpoint@1)!6iommu@ff470f00rockchip,iommuG N (aclkifacea < disabled!qos@ff518000rockchip,px30-qossysconQ !qos@ff520000rockchip,px30-qossysconR !#qos@ff52c000rockchip,px30-qossysconR !qos@ff538000rockchip,px30-qossysconS !qos@ff538080rockchip,px30-qossysconS !qos@ff538100rockchip,px30-qossysconS !qos@ff538180rockchip,px30-qossysconS !qos@ff540000rockchip,px30-qossysconT !qos@ff540080rockchip,px30-qossysconT !qos@ff548000rockchip,px30-qossysconT !qos@ff548080rockchip,px30-qossysconT !qos@ff548100rockchip,px30-qossysconT ! qos@ff548180rockchip,px30-qossysconT !!qos@ff548200rockchip,px30-qossysconT !"qos@ff550000rockchip,px30-qossysconU !qos@ff550080rockchip,px30-qossysconU !qos@ff550100rockchip,px30-qossysconU !qos@ff550180rockchip,px30-qossysconU !qos@ff558000rockchip,px30-qossysconU !qos@ff558080rockchip,px30-qossysconU !pinctrlrockchip,px30-pinctrl 4I+Vgpio0@ff040000rockchip,gpio-bank %]m!Egpio1@ff250000rockchip,gpio-bank% \]m!gpio2@ff260000rockchip,gpio-bank& ]]m!fgpio3@ff270000rockchip,gpio-bank' ^]mpcfg-pull-upy!pcfg-pull-downpcfg-pull-none!pcfg-pull-none-2mapcfg-pull-up-2maypcfg-pull-up-4may!pcfg-pull-none-4mapcfg-pull-down-4mapcfg-pull-none-8ma!pcfg-pull-up-8may!pcfg-pull-none-12ma !pcfg-pull-up-12may !pcfg-pull-none-smt!pcfg-output-highpcfg-output-lowpcfg-input-highy!pcfg-inputi2c0i2c0-xfer  !Di2c1i2c1-xfer !Ii2c2i2c2-xfer !Ji2c3i2c3-xfer   !Ktsadctsadc-otp-pin!]tsadc-otp-out!^uart0uart0-xfer   !'uart0-cts !(uart0-rts !)uart1uart1-xfer !7uart1-cts!8uart1-rts!9uart2-m0uart2m0-xfer uart2-m1uart2m1-xfer  !:uart3-m0uart3m0-xfer uart3m0-ctsuart3m0-rtsuart3-m1uart3m1-xfer !;uart3m1-cts !<uart3m1-rts !=uart4uart4-xfer !>uart4-cts!?uart4-rts!@uart5uart5-xfer !Auart5-cts!Buart5-rts!Cspi0spi0-clk!Lspi0-csn!Mspi0-miso !Nspi0-mosi !Ospi0-clk-hsspi0-miso-hs spi0-mosi-hs spi1spi1-clk!Pspi1-csn0 !Qspi1-csn1 !Rspi1-miso!Sspi1-mosi !Tspi1-clk-hsspi1-miso-hsspi1-mosi-hs pdmpdm-clk0m0pdm-clk0m1pdm-clk1pdm-sdi0m0pdm-sdi0m1pdm-sdi1pdm-sdi2pdm-sdi3pdm-clk0m0-sleeppdm-clk0m1-sleeppdm-clk1-sleeppdm-sdi0m0-sleeppdm-sdi0m1-sleeppdm-sdi1-sleeppdm-sdi2-sleeppdm-sdi3-sleepi2s0i2s0-8ch-mclki2s0-8ch-sclktxi2s0-8ch-sclkrx i2s0-8ch-lrcktxi2s0-8ch-lrckrx i2s0-8ch-sdo0i2s0-8ch-sdo1i2s0-8ch-sdo2i2s0-8ch-sdo3i2s0-8ch-sdi0i2s0-8ch-sdi1 i2s0-8ch-sdi2 i2s0-8ch-sdi3i2s1i2s1-2ch-mclki2s1-2ch-sclk!*i2s1-2ch-lrck!+i2s1-2ch-sdi!,i2s1-2ch-sdo!-i2s2i2s2-2ch-mclki2s2-2ch-sclk!.i2s2-2ch-lrck!/i2s2-2ch-sdi!0i2s2-2ch-sdo!1sdmmcsdmmc-clk!gsdmmc-cmd!hsdmmc-det!isdmmc-bus1sdmmc-bus4@!jsdiosdio-clk!msdio-cmd!lsdio-bus4@!kemmcemmc-clk !oemmc-cmd !pemmc-rstnout emmc-bus1emmc-bus4@emmc-bus8!qflashflash-cs0!uflash-rdy !wflash-dqs !yflash-ale !rflash-cle !tflash-wrn !xflash-cslflash-rdn!vflash-bus8!slcdclcdc-rgb-dclk-pinlcdc-rgb-m0-hsync-pinlcdc-rgb-m0-vsync-pinlcdc-rgb-m0-den-pinlcdc-rgb888-m0-data-pins     lcdc-rgb666-m0-data-pins      lcdc-rgb565-m0-data-pins     lcdc-rgb888-m1-data-pins   lcdc-rgb666-m1-data-pins   lcdc-rgb565-m1-data-pins   pwm0pwm0-pin!Upwm1pwm1-pin!Vpwm2pwm2-pin !Wpwm3pwm3-pin!Xpwm4pwm4-pin!Ypwm5pwm5-pin!Zpwm6pwm6-pin![pwm7pwm7-pin!\gmacrmii-pins !dmac-refclk-12ma !emac-refclk cif-m0cif-clkout-m0 dvp-d2d9-m0   dvp-d0d1-m0  d10-d11-m0 cif-m1cif-clkout-m1dvp-d2d9-m1  dvp-d0d1-m1 d10-d11-m1 ispisp-prelightbtbt-enable-h!sdio-pwrseqwifi-enable-h!pmicpmic_int!Fvcc5v0-sysregulator-fixed vcc5v0_sys LK@!LK@!Gsdio-pwrseqmmc-pwrseq-simple (ext_clockPZdefaulth !nvcc3v3-btregregulator-gpio Zdefaulthbtreg-gpio-supply 2Z!2Z2Z .vcc3v3-rf-aux-modregulator-fixedvcc3v3_rf_aux_mod 2Z!2Z :Gxin32k fixed-clockxin32k!chosen Eserial2:115200n8 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1mmc1mmc2mmc0device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,grfrockchip,outputremote-endpointrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspend#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesresetsreset-namesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsbits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outphy-supplysnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiobus-widthfifo-depthmax-frequencycap-sd-highspeedcard-detect-delayvmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104cap-mmc-highspeedmmc-hs200-1_8viommus#iommu-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinspost-power-on-delay-msreset-gpiosenable-active-highenable-gpiovin-supplystdout-path