(@8&L(&$mediatek,mt8192-evbmediatek,mt8192 +!7MediaTek MT8192 evaluation boardoscillator0 fixed-clock=JZclk26mmoscillator1 fixed-clock=JZclk32kcpus+cpu@0ucpuarm,cortex-a55psciJec3@mcpu@100ucpuarm,cortex-a55psciJec3@m cpu@200ucpuarm,cortex-a55psciJec3@m cpu@300ucpuarm,cortex-a55psciJec3@m cpu@400ucpuarm,cortex-a76psciJfm cpu@500ucpuarm,cortex-a76psciJfm cpu@600ucpuarm,cortex-a76psciJfmcpu@700ucpuarm,cortex-a76psciJfmcpu-mapcluster0core0core1 core2 core3 cluster1core0 core1 core2core3l2-cache0cacheml2-cache1cacheml3-cachecachemidle-states arm,pscicpuoff_larm,idle-state7! mcpuoff_barm,idle-state#!mclusteroff_larm,idle-state<!\mclusteroff_barm,idle-state(! mpmu-a55arm,cortex-a55-pmu 2pmu-a76arm,cortex-a76-pmu 2psci arm,psci-1.0smctimerarm,armv8-timer @2   J]@soc+ simple-bus=interrupt-controller@c000000 arm,gic-v3DU l   2 mppi-partitionsinterrupt-partition-0 minterrupt-partition-1 mpinctrl@10005000mediatek,mt8192-pinctrlP]iocfg0iocfg_rmiocfg_bmiocfg_bliocfg_briocfg_lmiocfg_lbiocfg_rtiocfg_ltiocfg_tleintl2Dmtimer@10017000,mediatek,mt8192-timermediatek,mt6765-timerp2clk13mserial@11002000*mediatek,mt8192-uartmediatek,mt6577-uart 2m baudbusokayserial@11003000*mediatek,mt8192-uartmediatek,mt6577-uart02n baudbus disabledspi@1100a000(mediatek,mt8192-spimediatek,mt6765-spi+2 parent-clksel-clkspi-clk disabledspi@11010000(mediatek,mt8192-spimediatek,mt6765-spi+2 parent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8192-spimediatek,mt6765-spi+ 2 parent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8192-spimediatek,mt6765-spi+02 parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8192-spimediatek,mt6765-spi+2 parent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8192-spimediatek,mt6765-spi+2 parent-clksel-clkspi-clk disabledspi@1101d000(mediatek,mt8192-spimediatek,mt6765-spi+2 parent-clksel-clkspi-clk disabledspi@1101e000(mediatek,mt8192-spimediatek,mt6765-spi+2 parent-clksel-clkspi-clk disabledspi@11234000mediatek,mt8192-nor#@2  spisfaxi+disablei2c3@11cb0000mediatek,mt8192-i2c !s2s maindma+ disabledi2c7@11d00000mediatek,mt8192-i2c !v2w maindma+ disabledi2c8@11d01000mediatek,mt8192-i2c !w2x maindma+ disabledi2c9@11d02000mediatek,mt8192-i2c  !y2y maindma+ disabledi2c1@11d20000mediatek,mt8192-i2c !q2q maindma+ disabledi2c2@11d21000mediatek,mt8192-i2c !q2r maindma+ disabledi2c4@11d22000mediatek,mt8192-i2c  !s2t maindma+ disabledi2c5@11e00000mediatek,mt8192-i2c !u2u maindma+ disabledi2c0@11f00000mediatek,mt8192-i2c !p2p maindma+ disabledi2c6@11f01000mediatek,mt8192-i2c !u2v maindma+ disabledaliases/soc/serial@11002000chosenserial0:921600n8memory@40000000umemory@ compatibleinterrupt-parent#address-cells#size-cellsmodel#clock-cellsclock-frequencyclock-output-namesphandledevice_typeregenable-methodcpu-idle-statesnext-level-cachecapacity-dmips-mhzcpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinityreg-namesgpio-controller#gpio-cellsgpio-rangesclocksclock-namesstatusclock-divserial0stdout-path