8D( `google,hana-rev6google,hana-rev5google,hana-rev4google,hana-rev3google,hanamediatek,mt8173 + 7Google Hanaaliases=/soc/ovl@1400c000B/soc/ovl@1400d000G/soc/rdma@1400e000M/soc/rdma@1400f000S/soc/rdma@14010000Y/soc/wdma@14011000_/soc/wdma@14012000e/soc/color@14013000l/soc/color@14014000s/soc/split@14018000z/soc/split@14019000/soc/dpi@1401d000/soc/dsi@1401b000/soc/dsi@1401c000/soc/rdma@14001000/soc/rdma@14002000/soc/rsz@14003000/soc/rsz@14004000/soc/rsz@14005000/soc/wdma@14006000/soc/wrot@14007000/soc/wrot@14008000/soc/serial@11002000/soc/serial@11003000/soc/serial@11004000/soc/serial@11005000opp_table0operating-points-v2 opp-50700000084 xopp-702000000)׫ opp-1001000000; @opp-1105000000A@ehopp-1209000000H@opp-1300000000M|m opp-1508000000YAopp-1703000000e*opp_table1operating-points-v2 opp-50700000084 `opp-702000000)׫ :opp-1001000000; @%opp-1209000000H@@opp-1404000000SW]opp-1612000000`+opp-1807000000kopp-2106000000}*cpus+cpu-mapcluster0core0%core1%cluster1core0%core1%cpu@0)cpuarm,cortex-a5359psciGWf cpuintermediate  cpu@1)cpuarm,cortex-a5359psciGWf cpuintermediate  cpu@100)cpuarm,cortex-a7259psciGWfcpuintermediate   cpu@101)cpuarm,cortex-a7259psciGWfcpuintermediate   idle-statespscicpu-sleep-0arm,idle-state@"pmu_a53arm,cortex-a53-pmu9 Dpmu_a72arm,cortex-a72-pmu9  Dpsci#arm,psci-1.0arm,psci-0.2arm,psci@smcWckoscillator0 fixed-clockrclk26moscillator1 fixed-clockr}clk32koscillator2 fixed-clockrcpum_ckthermal-zonescpu_thermaltripstrip-point0`0passivetrip-point10passivecpu_crit08 0criticalcooling-mapsmap0 map1reserved-memory+ vpu_dma_mem_region@b7000000shared-dma-pool5P'1timerarm,armv8-timer 09   8soc+ simple-bus clock-controller@10000000mediatek,mt8173-topckgen5rpower-controller@10001000 mediatek,mt8173-infracfgsyscon5rOpower-controller@10003000mediatek,mt8173-pericfgsyscon50rOsyscfg_pctl_a@10005000%mediatek,mt8173-pctl-a-syscfgsyscon5Ppinctrl@1000b000mediatek,mt8173-pinctrl5\q$9%EC_INT_1V8SD_CD_LALC5514_IRQALC5650_IRQAP_FLASH_WP_LSFINSFCS0SFHOLDSFOUTSFCKWRAP_EVENT_S_EINT10PMU_INTI2S2_WS_ALC5650I2S2_BCK_ALC5650PWR_BTN_1V8DA9212_IRQIDDIGWATCHDOGCECHDMISCKHDMISDHTPLGMSDC3_DAT0MSDC3_DAT1MSDC3_DAT2MSDC3_DAT3MSDC3_CLKMSDC3_CMDUSB_C0_OC_FLAGBUSBA_OC1_LPS8640_1V2_ENABLETHERM_ALERT_NPANEL_LCD_POWER_ENANX7688_CHIP_PD_CEC_IN_RW_1V8ANX7688_1V_EN_CUSB_DP_HPD_CTPM_DAVINT_NMARVELL8897_IRQEN_USB_A0_PWRUSBA_A0_OC_LEN_PP3300_DX_EDPSOC_I2C2_1V8_SDA_400KSOC_I2C2_1V8_SCL_400KSOC_I2C0_1V8_SDA_400KSOC_I2C0_1V8_SCL_400KEMMC_ID1EMMC_ID0MEM_CONFIG3EMMC_ID2MEM_CONFIG1MEM_CONFIG2BRD_ID2MEM_CONFIG0BRD_ID0BRD_ID1EMMC_DAT0EMMC_DAT1EMMC_DAT2EMMC_DAT3EMMC_DAT4EMMC_DAT5EMMC_DAT6EMMC_DAT7EMMC_CLKEMMC_CMDEMMC_RCLKPLT_RST_LLID_OPEN_1V8_LAUDIO_SPI_MISO_RAC_OK_1V8SD_DATA0SD_DATA1SD_DATA2SD_DATA3SD_CLKSD_CMDPWRAP_SPI0_MIPWRAP_SPI0_MOPWRAP_SPI0_CKPWRAP_SPI0_CSNWIFI_PDNRTC32K_1V8DISP_PWM0TOUCHSCREEN_INT_LSRCLKENA0SRCLKENA1PS8640_MODE_CONFTOUCHSCREEN_RESET_RPLATFORM_PROCHOT_LPANEL_POWER_ENREC_MODE_LEC_FW_UPDATE_LACCEL2_INT_LHDMI_DP_INTACCELGYRO3_INT_LACCELGYRO4_INT_LSPI_EC_CLKSPI_EC_MISPI_EC_MOSPI_EC_CSNSOC_I2C3_1V8_SDA_400KSOC_I2C3_1V8_SCL_400KPS8640_SYSRSTN_1V8APIN_MAX98090_DOUT2TP_INT_1V8_L_RRST_USB_HUB_RBT_WAKE_LACCEL1_INT_LTABLET_MODE_LV_UP_IN_L_RV_DOWN_IN_L_RSOC_I2C1_1V8_SDA_1MSOC_I2C1_1V8_SCL_1MPS8640_PDN_1V8MAX98090_LRCLKMAX98090_BCLKMAX98090_MCLKAPOUT_MAX98090_DINAPIN_MAX98090_DOUTSOC_I2C4_1V8_SDA_400KSOC_I2C4_1V8_SCL_400KxxxKpins1i2c0pins1-.i2c1&pins1}~da9211_pinsi2c2'pins1+,i2c3,pins1jki2c4pins1i2c6/pins1deaud_i2s2bpins1  bl_fixed_pinsVpins1 bt_wake_pinspins1wdisp_pwm0_pinsUpins1Wgpio_keys_pinsWvolume_pins{|tablet_mode_pinsyhdmi_mux_pinspins1$pins2bmmc0default1pins_cmd_dat$9:;<=>?@Bpins_clkApins_rstDmmc1default5pins_cmd_datIJKLN)fpins_clkM)pins_insertpins_wp*mmc3default9pins_dat)fpins_cmd)fpins_clk)mmc02pins_cmd_dat$9:;<=>?@B)epins_clkA)epins_dsC) epins_rstDmmc16pins_cmd_datIJKLN)fpins_clkM)fmmc3:pins_dat)fpins_cmd)fpins_clk)fnor+pins1 )pins2)pins_clk )panel_fixed_pins\pins1)ps8640_pins!pins1 \sps8640_fixed_pins]pins1rt5650_irq pins1sdio_fixed_3v3_pins^pins1Uspi1(pins1pins_spifghitrackpad_irq-pins1uusbApins1ewifi_wake_pinspins1&power-controller@10006000mediatek,mt8173-scpsys85`UXimfgmmvencvenc_ltL0watchdog@10007000(mediatek,mt8173-wdtmediatek,mt6589-wdt5ptimer@10008000,mediatek,mt8173-timermediatek,mt6577-timer5 9 xpwrap@1000d000mediatek,mt8173-pwrap5Upwrap 9_fpwrap   spiwrapmt6397mediatek,mt6397+ 9 mt6397clockmediatek,mt6397-clkrpinctrlmediatek,mt6397-pinctrlqmt6397regulatormediatek,mt6397-regulatorbuck_vpca15 rbuck_vpca15vpca15 `p0 buck_vpca7 rbuck_vpca7vpca7 `p0sbuck_vsramca15rbuck_vsramca15 vsramca15 `p0buck_vsramca7rbuck_vsramca7 vsramca7 `p0 buck_vcore rbuck_vcorevcore `p0buck_vgpu rbuck_vgpuvgpu `p0sbuck_vdrm rbuck_vdrmvdrmO\0buck_vio18 rbuck_vio18vio18 6`04ldo_vtcxo rldo_vtcxovtcxoldo_va28 rldo_va28va28ldo_vcama rldo_vcamavcamaw@w@ldo_vio28 rldo_vio28vio28ldo_vusb rldo_vusbvusb@ldo_vmcrldo_vmcvmcw@2Z8ldo_vmch rldo_vmchvmch-2Z7ldo_vemc3v3 rldo_vemc3v3 vemc_3v3-2Z3ldo_vgp1 rldo_vgp1vcamdw@w@ldo_vgp2 rldo_vgp2vcamio2Z2Z#ldo_vgp3 rldo_vgp3vcamafw@w@<ldo_vgp4 rldo_vgp4vgp4O2Zldo_vgp5 rldo_vgp5vgp5O-ldo_vgp6 rldo_vgp6vgp62Z2Z.ldo_vibr rldo_vibrvibr 2Zmt6397rtcmediatek,mt6397-rtcsyscfg_pctl_pmic@c000(mediatek,mt6397-pctl-pmic-syscfgsyscon5cec@10013000mediatek,mt8173-cec50 9 #okayvpu@10020000mediatek,mt8173-vpu 5 Utcmcfg_reg 9gmain*Eintpol-controller@10200620.mediatek,mt8173-sysirqmediatek,mt6577-sysirq 5  iommu@10205000mediatek,mt8173-m4u5 P 9bclk8GDefuse@10206000mediatek,mt8173-efuse5 `+calib@5285( *clock-controller@10209000mediatek,mt8173-apmixedsys5 rhdmi-phy@10209100mediatek,mt8173-hdmi-phy5 $pll_refhdmitx_dig_ctsT cru#okayLmailbox@10212000mediatek,mt8173-gce5!  9gceBmipi-dphy@10215000mediatek,mt8173-mipi-tx5!P mipi_tx0_pllru#okayFmipi-dphy@10216000mediatek,mt8173-mipi-tx5!` mipi_tx1_pllru #disabledHinterrupt-controller@10221000 arm,gic-400 @5"" "@ "`  9 auxadc@11001000mediatek,mt8173-auxadc5main)serial@11002000*mediatek,mt8173-uartmediatek,mt6577-uart5  9S$ baudbus#okayserial@11003000*mediatek,mt8173-uartmediatek,mt6577-uart50 9T% baudbus #disabledserial@11004000*mediatek,mt8173-uartmediatek,mt6577-uart5@ 9U& baudbus #disabledserial@11005000*mediatek,mt8173-uartmediatek,mt6577-uart5P 9V' baudbus #disabledi2c@11007000mediatek,mt8173-i2c 5pp 9L  maindmadefault+#okay @Yaudio-codec@1arealtek,rt56505 9default _edp-bridge@8parade,ps86405  !sdefault!-":#ports+port@05endpointG$Gport@15endpointG%[i2c@11008000mediatek,mt8173-i2c 5p 9M  maindmadefault&+#okay`da9211@68 dlg,da92115h 9regulatorsBUCKAVBUCKA `0WnC#' BUCKBVBUCKB `0Wn-'i2c@11009000mediatek,mt8173-i2c 5p 9N  maindmadefault'+#okaytpm@20infineon,slb9645tt5 spi@1100a000mediatek,mt8173-spi+5 9n4\parent-clksel-clkspi-clk#okaydefault(ec@0google,cros-ec-spi5 9i2c-tunnel0google,cros-ec-i2c-tunnel+sbs-battery@bsbs,sbs-battery5 keyboard-controllergoogle,cros-ec-keyb+ >DX};0DY1 d>"A#( C  \=@V B |})<?   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ithermal@1100b000emediatek,mt8173-thermal5 9F thermauxadc_{)*calibration-data  spi@1100d000mediatek,mt8173-nor5!rspisf+#okaydefault+flash@0jedec,spi-nor5i2c@11010000mediatek,mt8173-i2c 5p 9O  maindmadefault,+#okaytouchscreen@10elan,ekth35005 9Xtouchscreen@34melfas,mip4_ts54 9Xtouchscreen@20 hid-over-i2c5   9Xi2c@11011000mediatek,mt8173-i2c 5p 9P  maindmadefault-+#okaytrackpad@15elan,ekth3000 9u5.trackpad@2c hid-over-i2c 9u5, i2c@11012000mediatek,mt8173-hdmi-ddc 9Q5 ddc-i2cci2c@11013000mediatek,mt8173-i2c 50p 9R#  maindmadefault/+ #disabledaudio-controller@11220000mediatek,mt8173-afe-pcm5" 90Pdeybinfra_sys_audio_clktop_pdn_audiotop_pdn_aud_intbusbck0bck1i2s0_mi2s1_mi2s2_mi2s3_mi2s3_b mnammc@11230000mediatek,mt8173-mmc5# 9G_ sourcehclk#okaydefaultstate_uhs132= GYhw@3 4 `& mmc@11240000mediatek,mt8173-mmc5$ 9HR sourcehclk#okaydefaultstate_uhs536=   , 9 G7 8 P*mmc@11250000mediatek,mt8173-mmc5% 9IR sourcehclk #disabledmmc@11260000mediatek,mt8173-mmc5& 9Ju sourcehclk#okaydefaultstate_uhs93:=   , 9 Y o ; <  +btmrvl@2marvell,sd8897-bt5 9w  dmwifiex@1marvell,sd88975 9& usb@11271000mediatek,mt8173-mtu3 5'0( Umacippc 9@ =>?0 ^sys_ckref_ck + #okay host @xhci@11270000mediatek,mt8173-xhci5'Umac 9s0 ^sys_ckref_ck#okaydefaultA @usb-phy@11290000mediatek,mt8173-u3phy5)+ #okayusb-phy@112908005)refu#okay=usb-phy@112909005) refu#okay>usb-phy@112910005)refu#okay?syscon@14000000mediatek,mt8173-mmsyssyscon50 U ׄr BB BCrdma@14001000-mediatek,mt8173-mdp-rdmamediatek,mt8173-mdp5CC0 1D 8 FErdma@14002000mediatek,mt8173-mdp-rdma5 CC0 1D 8rsz@14003000mediatek,mt8173-mdp-rsz50C0rsz@14004000mediatek,mt8173-mdp-rsz5@C0rsz@14005000mediatek,mt8173-mdp-rsz5PC0wdma@14006000mediatek,mt8173-mdp-wdma5`C 0 1D 8wrot@14007000mediatek,mt8173-mdp-wrot5pC 0 1D 8wrot@14008000mediatek,mt8173-mdp-wrot5C 0 1D 8ovl@1400c000mediatek,mt8173-disp-ovl5 90C 1D 8 Bovl@1400d000mediatek,mt8173-disp-ovl5 90C 1D 8 Brdma@1400e000mediatek,mt8173-disp-rdma5 90C 1D 8 Brdma@1400f000mediatek,mt8173-disp-rdma5 90C 1D 8 Brdma@14010000mediatek,mt8173-disp-rdma5 90C 1D 8 Bwdma@14011000mediatek,mt8173-disp-wdma5 90C 1D 8 Bwdma@14012000mediatek,mt8173-disp-wdma5  90C 1D 8 B color@14013000mediatek,mt8173-disp-color50 90C B0color@14014000mediatek,mt8173-disp-color5@ 90C B@aal@14015000mediatek,mt8173-disp-aal5P 90C BPgamma@14016000mediatek,mt8173-disp-gamma5` 90C B`merge@14017000mediatek,mt8173-disp-merge5p0Csplit@14018000mediatek,mt8173-disp-split50Csplit@14019000mediatek,mt8173-disp-split50Cufoe@1401a000mediatek,mt8173-disp-ufoe5 90Cdsi@1401b000mediatek,mt8173-dsi5 90C$C%Fenginedigitalhs F Sdphy#okayportsportendpointGG$dsi@1401c000mediatek,mt8173-dsi5 90C&C'Henginedigitalhs H Sdphy #disableddpi@1401d000mediatek,mt8173-dpi5 90C(C)pixelenginepll#okayportendpointGIMpwm@1401e0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm5 ]C!C mainmm#okaySpwm@1401f0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm5 ]C#C"mainmm #disabledmutex@14020000mediatek,mt8173-disp-mutex5 90C h56larb@14021000mediatek,mt8173-smi-larb5 |J0CCapbsmismi@14022000mediatek,mt8173-smi-common5 0CCapbsmiJod@14023000mediatek,mt8173-disp-od50Chdmi@14025000mediatek,mt8173-hdmi5P 9 C,C-C.C/pixelpllbclkspdifdefaultK L Shdmi C  sL#okay`ports+port@05endpointGMIport@15endpointGNdlarb@14027000mediatek,mt8173-smi-larb5p |J0C2C2apbsmiclock-controller@15000000mediatek,mt8173-imgsyssyscon5rOlarb@15001000mediatek,mt8173-smi-larb5 |J0OOapbsmiclock-controller@16000000mediatek,mt8173-vdecsyssyscon5rPvcodec@16000000mediatek,mt8173-vcodec-dec5 0@Phpx 9 8@ 1D D!D%D&D'D"D#D$ FE0@ >lWMiNZvcodecpllunivpll_d2clk_cci400_selvdec_selvdecpllvencpllvenc_lt_selvdec_bus_clk_src( ilW N>M XU/larb@16010000mediatek,mt8173-smi-larb5 |J0PPapbsmiclock-controller@18000000mediatek,mt8173-vencsyssyscon5rQlarb@18001000mediatek,mt8173-smi-larb5 |J0QQapbsmivcodec@18002000mediatek,mt8173-vcodec-enc 5  9 8 1D`DaDbDcDdDiDjDkDlDmDnDDDDDDDDD FE PX?i2venc_sel_srcvenc_selvenc_lt_sel_srcvenc_lt_sel XiMNjpegdec@18004000mediatek,mt8173-jpgdec5@ 9QQjpgdec-smijpgdec0 8 1DgDhclock-controller@19000000!mediatek,mt8173-vencltsyssyscon5rRlarb@19001000mediatek,mt8173-smi-larb5 |J0RRapbsmimemory@40000000)memory5@backlightpwm-backlight SB@ T _defaultU#okayZfixedregulator2regulator-fixed bl_fixedw@w@    defaultVTchosen serial0:115200n8gpio-keys gpio-keysdefaultWlid Lid E   power Power  t $ tablet_mode Tablet_mode y   volume_down Volume_down { rvolume_up Volume_up | spanel lg,lp120up1 X 6Y BZportendpointG[%regulator1regulator-fixed PANEL_3V32Z2Z  )default\Xregulator2regulator-fixed PS8640_1V2OO  L default]"fixedregulator0regulator-fixed3V32Z2Z Udefault^;soundmediatek,mt8173-rt5650 ^_` sadefaultb codec-capture _connectorhdmi-connector hdmi0a 6cportendpointGdN compatibleinterrupt-parent#address-cells#size-cellsmodelovl0ovl1rdma0rdma1rdma2wdma0wdma1color0color1split0split1dpi0dsi0dsi1mdp-rdma0mdp-rdma1mdp-rsz0mdp-rsz1mdp-rsz2mdp-wdma0mdp-wrot0mdp-wrot1serial0serial1serial2serial3opp-sharedphandleopp-hzopp-microvoltcpudevice_typeregenable-methodcpu-idle-states#cooling-cellsdynamic-power-coefficientclocksclock-namesoperating-points-v2capacity-dmips-mhzproc-supplysram-supplyentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paraminterruptsinterrupt-affinitycpu_suspendcpu_offcpu_on#clock-cellsclock-frequencyclock-output-namespolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionrangesalignmentno-maparm,no-tick-in-suspend#reset-cellsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsgpio-line-namespinmuxinput-enablebias-pull-downbias-disablebias-pull-upoutput-lowoutput-highdrive-strength#power-domain-cellsinfracfgreg-namesresetsreset-namesregulator-compatibleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-allowed-modesregulator-enable-ramp-delaystatusmemory-regionmediatek,larbs#iommu-cellsmediatek,ibiasmediatek,ibias_up#phy-cells#mbox-cells#io-channel-cellsclock-divpinctrl-namespinctrl-0avdd-supplycpvdd-supply#sound-dai-cellsrealtek,dmic1-data-pinrealtek,jd-modepowerdown-gpiosreset-gpiosvdd12-supplyvdd33-supplyremote-endpointregulator-min-microampregulator-max-microamppowered-while-suspendedmediatek,pad-selectspi-max-frequencygoogle,cros-ec-spi-msg-delaygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymap#thermal-sensor-cellsmediatek,auxadcmediatek,apmixedsysnvmem-cellsnvmem-cell-namesbank0-supplybank1-supplyhid-descr-addrvcc-supplywakeup-sourcepower-domainsassigned-clocksassigned-clock-parentspinctrl-1bus-widthcap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-reseths400-ds-delaymediatek,hs200-cmd-int-delaymediatek,hs400-cmd-int-delaymediatek,hs400-cmd-resp-sel-risingvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104cd-gpioswp-gpioskeep-power-in-suspendenable-sdio-wakeupcap-sdio-irqcap-power-off-cardmarvell,wakeup-pinmarvell,wakeup-gap-msphysmediatek,syscon-wakeupdr_modevusb33-supplyassigned-clock-ratesmboxesmediatek,gce-client-regiommusmediatek,larbmediatek,vpuphy-names#pwm-cellsmediatek,gce-eventsmediatek,smimediatek,syscon-hdmipwmspower-supplyenable-gpiosstartup-delay-usenable-active-highgpiostdout-pathlabellinux,codelinux,input-typegpio-key,wakeupdebounce-intervalddc-i2c-busbacklightregulator-boot-onmediatek,audio-codecmediatek,platformmediatek,mclksound-dai