w8( p-hardkernel,rk3326-odroid-go2rockchip,rk3326 +7ODROID-GO Advancealiases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000/serial@ff178000/spi@ff1d0000/spi@ff1d8000/mmc@ff370000cpus+cpu@0cpuarm,cortex-a35psciZ cpu@1cpuarm,cortex-a35psciZ cpu@2cpuarm,cortex-a35psciZ  cpu@3cpuarm,cortex-a35psciZ  idle-statespscicpu-sleeparm,idle-state,=Txeucluster-sleeparm,idle-state,=Teucpu0-opp-tableoperating-points-v2opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem okayexternal-gmac-clock fixed-clock gmac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal4BT tripstrip-point-0dpppassivetrip-point-1dLppassive soc-critd8p criticalcooling-mapsmap0{  map1{  gpu-thermald4T xin24m fixed-clockn6xin24m^power-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+`power-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !power-domain@14I"syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+io-domains$rockchip,px30-pmu-io-voltage-domainokay##reboot-modesyscon-reboot-modeRBRB RBRBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart $$baudclkapb_pclk*%%/txrx9CPdefault ^&'( disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  i2s_clki2s_hclk*%%/txrxPdefault^)*+,hokayi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s i2s_clki2s_hclk*%%/txrxPdefault^-./0h disabledinterrupt-controller@ff131000 arm,gic-400y@ @ `   syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+4io-domains rockchip,px30-io-voltage-domainokay121111lvdsrockchip,px30-lvds3dphy4lvds disabledports+port@0+endpoint@05serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart Ibaudclkapb_pclk*%%/txrx9CPdefault^67okayserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart Jbaudclkapb_pclk*%%/txrx9CPdefault^8okayserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart Kbaudclkapb_pclk*%%/txrx9CPdefault ^9:; disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart Lbaudclkapb_pclk*%% /txrx9CPdefault ^<=> disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart Mbaudclkapb_pclk*% % /txrx9CPdefault ^?@A disabledi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN i2cpclk Pdefault^B+okay/Gpmic@20rockchip,rk817  C rk808-clkout1xin32kmclkPdefault^DE^hlFxFFFFFFregulatorsDCDC_REG1 vdd_logic~0q(yregulator-state-mem:R~DCDC_REG2vdd_arm~pq(regulator-state-memnR~DCDC_REG3vcc_ddr(regulator-state-mem:DCDC_REG4vcc_3v32Z2Z(1regulator-state-memnR2ZLDO_REG2vcc_1v8w@w@(]regulator-state-mem:Rw@LDO_REG3vdd_1v0B@B@(regulator-state-mem:RB@LDO_REG4 vcc3v3_pmu2Z2Z(#regulator-state-mem:R2ZLDO_REG5 vccio_sdw@2Z(2regulator-state-mem:R2ZLDO_REG6vcc_sd2Z2Z(iregulator-state-mem:R2ZLDO_REG7vcc_bl2Z2Zregulator-state-memnR2ZLDO_REG8vcc_lcd**}regulator-state-memnR*LDO_REG9vcc_cam--regulator-state-memnR-codeci2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO i2cpclk Pdefault^G+okayi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP i2cpclk  Pdefault^H+ disabledi2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q i2cpclk  Pdefault^I+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $Uspiclkapb_pclk*% % /txrxPdefault^JKLM+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %Vspiclkapb_pclk*%%/txrxPdefault^NOPQR+ disabledwatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ % disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkPdefault^S disabledpwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkPdefault^Tokaypwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkPdefault^U disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S pwmpclkPdefault^V disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkPdefault^W disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkPdefault^X disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkPdefault^Y disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T pwmpclkPdefault^Z disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& pclktimerdmac@ff240000arm,pl330arm,primecell$@ apb_pclk%tsadc@ff280000rockchip,px30-tsadc( $,P,Xtsadcapb_pclk tsadc-apb4 Pinitdefaultsleep^[ \*[4okay saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( TJ-Wsaradcapb_pclk saradc-apbokay\]nvmem@ff290000rockchip,px30-otp)@/Zaotpapb_pclkphyphy+id@7cpu-leakage@17performance@1ehclock-controller@ff2b0000rockchip,px30-cru+ ^$ xin24mgpll4m@@I Fq рр f@clock-controller@ff2bc000rockchip,px30-pmucru+^xin24m4m$$$ G$syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy $ phyclkz_ usb480m_phyokay_host-port D linestateokaybotg-port$BA@otg-bvalidotg-idlinestate disabledaphy@ff2e0000rockchip,px30-dsi-dphy.$ E refpclk>apb` okay3usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >otgotg@ a usb2-phy`okayusb@ff340000 generic-ehci4 <busb` disabledusb@ff350000 generic-ohci5 =busb` disabledethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed4rmiiPdefault^cd` ^ stmmaceth disabledmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CDbiuciuciu-driveciu-sampleрPdefault^efgh`okay/ ACJWdqi2mmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EFbiuciuciu-driveciu-sampleрPdefault ^jkl`  disabledmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GHbiuciuciu-driveciu-sampleрPdefault ^mno`  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 97ahbnfc7рPdefault ^pqrstuvw`  disabledopp-table2operating-points-v2xopp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuI`xokayydsi@ff450000rockchip,px30-mipi-dsiE KDpclk3dphy` =apb4+okayports+port@0+endpoint@0zport@1endpoint{panel@0elida,kd35t133|} ~}portendpoint{vop@ff460000rockchip,px30-vop-bigF Maclk_vopdclk_vophclk_vop345 axiahbdclk` okayport+ endpoint@0zendpoint@15iommu@ff460f00rockchip,iommuF M aclkiface` okayqos@ff518000rockchip,px30-qossysconQ qos@ff520000rockchip,px30-qossysconR "qos@ff52c000rockchip,px30-qossysconR qos@ff538000rockchip,px30-qossysconS qos@ff538080rockchip,px30-qossysconS qos@ff538100rockchip,px30-qossysconS qos@ff538180rockchip,px30-qossysconS qos@ff540000rockchip,px30-qossysconT qos@ff540080rockchip,px30-qossysconT qos@ff548000rockchip,px30-qossysconT qos@ff548080rockchip,px30-qossysconT qos@ff548100rockchip,px30-qossysconT qos@ff548180rockchip,px30-qossysconT  qos@ff548200rockchip,px30-qossysconT !qos@ff550000rockchip,px30-qossysconU qos@ff550080rockchip,px30-qossysconU qos@ff550100rockchip,px30-qossysconU qos@ff550180rockchip,px30-qossysconU qos@ff558000rockchip,px30-qossysconU qos@ff558080rockchip,px30-qossysconU pinctrlrockchip,px30-pinctrl4+gpio0@ff040000rockchip,gpio-bank $yCgpio1@ff250000rockchip,gpio-bank% \ygpio2@ff260000rockchip,gpio-bank& ]ygpio3@ff270000rockchip,gpio-bank' ^y~pcfg-pull-uppcfg-pull-down,pcfg-pull-none;pcfg-pull-none-2ma;Hpcfg-pull-up-2maHpcfg-pull-up-4maHpcfg-pull-none-4ma;Hpcfg-pull-down-4ma,Hpcfg-pull-none-8ma;Hpcfg-pull-up-8maHpcfg-pull-none-12ma;H pcfg-pull-up-12maH pcfg-pull-none-smt;Wpcfg-output-highlpcfg-output-lowxpcfg-input-highpcfg-inputi2c0i2c0-xfer  Bi2c1i2c1-xfer Gi2c2i2c2-xfer Hi2c3i2c3-xfer   Itsadctsadc-otp-pin[tsadc-otp-out\uart0uart0-xfer   &uart0-cts 'uart0-rts (uart1uart1-xfer 6uart1-cts7uart1-rtsuart2-m0uart2m0-xfer uart2-m1uart2m1-xfer  8uart3-m0uart3m0-xfer uart3m0-ctsuart3m0-rtsuart3-m1uart3m1-xfer 9uart3m1-cts :uart3m1-rts ;uart4uart4-xfer <uart4-cts=uart4-rts>uart5uart5-xfer ?uart5-cts@uart5-rtsAspi0spi0-clkJspi0-csnKspi0-miso Lspi0-mosi Mspi0-clk-hsspi0-miso-hs spi0-mosi-hs spi1spi1-clkNspi1-csn0 Ospi1-csn1 Pspi1-misoQspi1-mosi Rspi1-clk-hsspi1-miso-hsspi1-mosi-hs pdmpdm-clk0m0pdm-clk0m1pdm-clk1pdm-sdi0m0pdm-sdi0m1pdm-sdi1pdm-sdi2pdm-sdi3pdm-clk0m0-sleeppdm-clk0m1-sleeppdm-clk1-sleeppdm-sdi0m0-sleeppdm-sdi0m1-sleeppdm-sdi1-sleeppdm-sdi2-sleeppdm-sdi3-sleepi2s0i2s0-8ch-mclki2s0-8ch-sclktxi2s0-8ch-sclkrx i2s0-8ch-lrcktxi2s0-8ch-lrckrx i2s0-8ch-sdo0i2s0-8ch-sdo1i2s0-8ch-sdo2i2s0-8ch-sdo3i2s0-8ch-sdi0i2s0-8ch-sdi1 i2s0-8ch-sdi2 i2s0-8ch-sdi3i2s1i2s1-2ch-mclkEi2s1-2ch-sclk)i2s1-2ch-lrck*i2s1-2ch-sdi+i2s1-2ch-sdo,i2s2i2s2-2ch-mclki2s2-2ch-sclk-i2s2-2ch-lrck.i2s2-2ch-sdi/i2s2-2ch-sdo0sdmmcsdmmc-clkesdmmc-cmdfsdmmc-detgsdmmc-bus1sdmmc-bus4@hsdiosdio-clklsdio-cmdksdio-bus4@jemmcemmc-clk memmc-cmd nemmc-rstnout emmc-bus1emmc-bus4@emmc-bus8oflashflash-cs0sflash-rdy uflash-dqs wflash-ale pflash-cle rflash-wrn vflash-cslflash-rdntflash-bus8qlcdclcdc-rgb-dclk-pinlcdc-rgb-m0-hsync-pinlcdc-rgb-m0-vsync-pinlcdc-rgb-m0-den-pinlcdc-rgb888-m0-data-pins     lcdc-rgb666-m0-data-pins      lcdc-rgb565-m0-data-pins     lcdc-rgb888-m1-data-pins   lcdc-rgb666-m1-data-pins   lcdc-rgb565-m1-data-pins   pwm0pwm0-pinSpwm1pwm1-pinTpwm2pwm2-pin Upwm3pwm3-pinVpwm4pwm4-pinWpwm5pwm5-pinXpwm6pwm6-pinYpwm7pwm7-pinZgmacrmii-pins cmac-refclk-12ma dmac-refclk cif-m0cif-clkout-m0 dvp-d2d9-m0   dvp-d0d1-m0  d10-d11-m0 cif-m1cif-clkout-m1dvp-d2d9-m1  dvp-d0d1-m1 d10-d11-m1 ispisp-prelightbtnsbtn-pins  headphonehp-detledsblue-led-pinpmicdc-det pmic-int Dsoc_slppin_gpiosoc_slppin_rstsoc_slppin_slpchosenserial2:115200n8adc-joystick adc-joystick+axis@0  axis@1  /backlightpwm-backlighta|gpio-keys gpio-keysPdefault^sw1 D DPAD-UP sw2 D  DPAD-DOWN!sw3 D DPAD-LEFT"sw4 D DPAD-RIGHT#sw5 DBTN-A1sw6 DBTN-B0sw7 DBTN-Y4sw8 DBTN-X3sw9 DF1sw10 DF2sw11 DF3sw12 DF4sw13 DF5sw14 DF6sw15 D TOP-LEFT6sw16 D TOP-RIGHT7gpio-leds gpio-ledsPdefault^led-0blue:heartbeat DC heartbeatrk817-soundsimple-audio-card Analog "i2s ; Y9 sMicrophoneMic JackHeadphoneHeadphonesSpeakerSpeaker; MICLMic JackHeadphonesHPOLHeadphonesHPORSpeakerSPKOsimple-audio-card,codec simple-audio-card,cpu vccsysregulator-fixed vcc3v8_sys99Fvcc_hostregulator-fixed vcc_hostLK@LK@ TC  F compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1mmc0device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,grfrockchip,outputremote-endpointi2c-scl-falling-time-nsi2c-scl-rising-time-nswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendrockchip,mic-in-differential#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesresetsreset-namesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modebus-widthfifo-depthmax-frequencycap-sd-highspeedcard-detect-delaycd-gpiossd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymali-supplybacklightiovcc-supplyreset-gpiosrotationvdd-supplyiommus#iommu-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsabs-flatabs-fuzzabs-rangelinux,codepower-supplypwmslabellinux,default-triggersimple-audio-card,namesimple-audio-card,formatsimple-audio-card,hp-det-gpiosimple-audio-card,mclk-fssimple-audio-card,widgetssimple-audio-card,routingsound-daienable-active-highvin-supply