z'8s(?s&firefly,roc-rk3308-ccrockchip,rk3308 +7Firefly ROC-RK3308-CC boardaliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000/spi@ff140000/mmc@ff480000/mmc@ff490000cpus+cpu@0cpuarm,cortex-a35psciZ cpu@1cpuarm,cortex-a35psci cpu@2cpuarm,cortex-a35psci cpu@3cpuarm,cortex-a35psci idle-states(pscicpu-sleeparm,idle-state5F]xn~ l2-cachecache cpu0-opp-tableoperating-points-v2 opp-408000000Q ~~r`@opp-600000000#F ~~r`@opp-8160000000, r`@opp-1008000000< **r`@arm-pmuarm,cortex-a35-pmu0STUV external-mac-clock fixed-clock mac_clkin psci arm,psci-1.0smctimerarm,armv8-timer0   xin24m fixed-clock n6xin24mgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfd Nreboot-modesyscon-reboot-mode!RB1RB=RBIRBWRB syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfd@+usb2phy@100rockchip,rk3308-usb2phyeu Hphyclk usb480m_phy  disabled otg-port$CDEotg-bvalidotg-idlinestate disabled :host-port J linestate disabled ;syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default + disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default +okayrtc@51 nxp,pcf8563Q i2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default+ disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk default+ disabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt   disabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault  disabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault  disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefaultokayserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart baudclkapb_pclkdefault  disabledspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclktxrxdefault disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclktxrxdefault !"# disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclk$$txrxdefault%&'( disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault) disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault* disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm y pwmpclkdefault+ disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm0y pwmpclkdefault, disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkdefault- disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkactive.okay \pwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm x pwmpclkdefault/ disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm0x pwmpclkdefault0 disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault1okay apwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault2 disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm  pwmpclkdefault3 disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm0 pwmpclkdefault4 disabledrktimer@ff1a0000rockchip,rk3288-timer   pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc %%saradcapb_pclkF saradc-apb disableddma-controller@ff2c0000arm,pl330arm,primecell,@( apb_pclk? dma-controller@ff2d0000arm,pl330arm,primecell-@( apb_pclk? $i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s5 4\i2s_clki2s_hclk$$ txrxreset-mreset-hdefault5678 disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s6 5^i2s_clki2s_hclk$ rxreset-mreset-h disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif: 7b mclkhclk$ txdefault9 disabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2@ BotgJotgRds@ : usb2-phy disabledusb@ff440000 generic-ehciD G ;usb disabledusb@ff450000 generic-ohciE H ;usb disabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcH@ L 012biuciuciu-driveciu-sampleрdefault<=>?okay,@Ammc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcI@ M :;<biuciuciu-driveciu-sampleрokay*9mmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcJ@ N 567biuciuciu-driveciu-sampleрdefault BCD disablednand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfcK@ Q-ahbnfce-GрEFGHIJKdefault disabledethernet@ff4e0000rockchip,rk3308-gmacN @macirq@@BBA@C[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed\rmiidefaultLM} stmmacetheN disabledclock-controller@ff500000rockchip,rk3308-cruP reNeG interrupt-controller@ff580000 arm,gic-400@XX X@ X`    sram@fff80000 mmio-sram+ddr-sram@0vad-sram@8000pinctrlrockchip,rk3308-pinctrleN+defaultOgpio0@ff220000rockchip,gpio-bank" ( Zgpio1@ff230000rockchip,gpio-bank# )gpio2@ff240000rockchip,gpio-bank$ *gpio3@ff250000rockchip,gpio-bank% +gpio4@ff260000rockchip,gpio-bank& , _pcfg-pull-up Ypcfg-pull-down Vpcfg-pull-none Rpcfg-pull-none-2mapcfg-pull-up-2mapcfg-pull-up-4ma Xpcfg-pull-none-4ma Wpcfg-pull-down-4mapcfg-pull-none-8ma Ppcfg-pull-up-8ma Qpcfg-pull-none-12ma  Tpcfg-pull-up-12ma  Spcfg-pull-none-smt Upcfg-output-highpcfg-output-low!pcfg-input-high,pcfg-input,emmcemmc-clk9 Pemmc-cmd9Qemmc-pwren9 Remmc-rstn9 Remmc-bus19Qemmc-bus4@9QQQQemmc-bus89QQQQQQQQflashflash-csn09 R Hflash-rdy9 R Jflash-ale9 R Eflash-cle9 R Gflash-wrn9R Kflash-rdn9 R Iflash-bus89SSSSSSSS Fgmacrmii-pins9TTTRRRRR R Lmac-refclk-12ma9 T Mmac-refclk9 Rgmac-m1rmiim1-pins9TTTRRRRR Rmacm1-refclk-12ma9 Tmacm1-refclk9 Ri2c0i2c0-xfer 9UU i2c1i2c1-xfer 9 U U i2c2i2c2-xfer 9UU i2c3-m0i2c3m0-xfer 9UU i2c3-m1i2c3m1-xfer 9 U Ui2c3-m2i2c3m2-xfer 9UUi2s_2ch_0i2s-2ch-0-mclk9 Ri2s-2ch-0-sclk9 R 5i2s-2ch-0-lrck9R 6i2s-2ch-0-sdo9R 8i2s-2ch-0-sdi9R 7i2s_8ch_0i2s-8ch-0-mclk9Ri2s-8ch-0-sclktx9Ri2s-8ch-0-sclkrx9Ri2s-8ch-0-lrcktx9Ri2s-8ch-0-lrckrx9Ri2s-8ch-0-sdo09 Ri2s-8ch-0-sdo19 Ri2s-8ch-0-sdo29 Ri2s-8ch-0-sdo39 Ri2s-8ch-0-sdi09 Ri2s-8ch-0-sdi19Ri2s-8ch-0-sdi29Ri2s-8ch-0-sdi39Ri2s_8ch_1_m0i2s-8ch-1-m0-mclk9Ri2s-8ch-1-m0-sclktx9Ri2s-8ch-1-m0-sclkrx9Ri2s-8ch-1-m0-lrcktx9Ri2s-8ch-1-m0-lrckrx9Ri2s-8ch-1-m0-sdo09Ri2s-8ch-1-m0-sdo1-sdi39Ri2s-8ch-1-m0-sdo2-sdi29 Ri2s-8ch-1-m0-sdo3_sdi19 Ri2s-8ch-1-m0-sdi09 Ri2s_8ch_1_m1i2s-8ch-1-m1-mclk9 Ri2s-8ch-1-m1-sclktx9 Ri2s-8ch-1-m1-sclkrx9Ri2s-8ch-1-m1-lrcktx9Ri2s-8ch-1-m1-lrckrx9Ri2s-8ch-1-m1-sdo09Ri2s-8ch-1-m1-sdo1-sdi39Ri2s-8ch-1-m1-sdo2-sdi29Ri2s-8ch-1-m1-sdo3_sdi19Ri2s-8ch-1-m1-sdi09Rpdm_m0pdm-m0-clk9Rpdm-m0-sdi09 Rpdm-m0-sdi19 Rpdm-m0-sdi29 Rpdm-m0-sdi39Rpdm_m1pdm-m1-clk9Rpdm-m1-sdi09Rpdm-m1-sdi19Rpdm-m1-sdi29Rpdm-m1-sdi39Rpdm_m2pdm-m2-clkm9Rpdm-m2-clk9Rpdm-m2-sdi09 Rpdm-m2-sdi19Rpdm-m2-sdi29Rpdm-m2-sdi39Rpwm0pwm0-pin9 Rpwm0-pin-pull-down9 V 1pwm1pwm1-pin9R 2pwm1-pin-pull-down9Vpwm2pwm2-pin9R 3pwm2-pin-pull-down9Vpwm3pwm3-pin9R 4pwm3-pin-pull-down9Vpwm4pwm4-pin9R -pwm4-pin-pull-down9Vpwm5pwm5-pin9Rpwm5-pin-pull-down9V .pwm6pwm6-pin9R /pwm6-pin-pull-down9Vpwm7pwm7-pin9R 0pwm7-pin-pull-down9Vpwm8pwm8-pin9 R )pwm8-pin-pull-down9 Vpwm9pwm9-pin9 R *pwm9-pin-pull-down9 Vpwm10pwm10-pin9 R +pwm10-pin-pull-down9 Vpwm11pwm11-pin9R ,pwm11-pin-pull-down9Vrtcrtc-32k9R Osdmmcsdmmc-clk9W <sdmmc-cmd9X =sdmmc-det9X >sdmmc-pwren9Wsdmmc-bus19Xsdmmc-bus4@9XXXX ?sdiosdio-clk9P Dsdio-cmd9Q Csdio-pwren9Psdio-wrpt9Psdio-intn9Psdio-bus19Qsdio-bus4@9QQQQ Bspdif_inspdif-in9Rspdif_outspdif-out9R 9spi0spi0-clk9X spi0-csn09X spi0-miso9X spi0-mosi9X spi1spi1-clk9 X spi1-csn09 X !spi1-miso9 X "spi1-mosi9 X #spi1-m1spi1m1-miso9Xspi1m1-mosi9Xspi1m1-clk9Xspi1m1-csn09 Xspi2spi2-clk9X %spi2-csn09X &spi2-miso9X 'spi2-mosi9X (tsadctsadc-otp-pin9 Rtsadc-otp-out9 Ruart0uart0-xfer 9YY uart0-cts9R uart0-rts9R uart0-rts-pin9Ruart1uart1-xfer 9YY uart1-cts9R uart1-rts9R uart2-m0uart2m0-xfer 9YY uart2-m1uart2m1-xfer 9YYuart3uart3-xfer 9 Y Y uart3-m1uart3m1-xfer 9YYuart4uart4-xfer 9 YY uart4-cts9R uart4-rts9R uart4-rts-pin9Rir-receiverir-recv-pin9R [buttonspwr-key9YchosenGserial2:1500000n8ir_rxgpio-ir-receiver SZdefault[ir_tx pwm-ir-txY\aleds gpio-ledsled-0^firefly:red:powerdir-power-clickzon SZled-1^firefly:blue:userdir-user-clickzoff SZ typec-vcc5vregulator-fixed typec_vcc5vLK@LK@ ]vcc5v0-sysregulator-fixed vcc5v0_sysLK@LK@] ^vcc-ioregulator-fixedvcc_io2Z2Z^ `vcc-sdmmcregulator-gpio vcc_sdmmcw@2Z SZw@2Z^ Avcc-sdregulator-fixed _vcc_sd2Z2Z` @vdd-corepwm-regulatorYa vdd_core xr`|4^ vdd-logregulator-fixedvdd_log^ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesstatusinterrupt-names#phy-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesarm,pl330-periph-burst#dma-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removableassigned-clock-ratesphy-moderockchip,grf#reset-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathgpiospwmslabellinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioregulator-init-microvoltregulator-settling-time-up-uspwm-supply