8((X~pine64,rock64rockchip,rk3328 +7Pine64 Rock64aliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53xpscicpu@1}cpuarm,cortex-a53xpscicpu@2}cpuarm,cortex-a53xpscicpu@3}cpuarm,cortex-a53xpsci l2-cache0cacheopp_table0operating-points-v2opp-408000000Q~#@4opp-600000000#F~#@opp-8160000000,B@#@opp-1008000000<#@opp-1200000000G(#@opp-1296000000M?d #@amba simple-bus+@dmac@ff1f0000arm,pl330arm,primecell@G Rapb_pclk^ arm-pmuarm,cortex-a53-pmu0Gdefgi display-subsystemrockchip,display-subsystem| psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0G   xin24m fixed-clockn6xin24mAi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s G)7Ri2s_clki2s_hclk txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s G*8Ri2s_clki2s_hclk  txrxokayportdendpointi2s @i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s G+9Ri2s_clki2s_hclk txrx disabledspdif@ff030000rockchip,rk3328-spdif G.: Rmclkhclk txdefault okayporteendpointfpdm@ff040000 rockchip,pdm=RRpdm_clkpdm_hclk rxdefaultsleep  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd+6io-domains"rockchip,rk3328-io-voltage-domainokay,:HVdrgrf-gpiorockchip,rk3328-grf-gpiopower-controller!rockchip,rk3328-power-controller+8pd_hevc@6pd_video@5pd_vpu@8Freboot-modesyscon-reboot-modeRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart G7&Rbaudclkapb_pclk  txrxdefault   disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart G8'Rbaudclkapb_pclk  txrxdefault   ! disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart G9(Rbaudclkapb_pclk  txrxdefault "okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c G$+7 Ri2cpclkdefault # disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c G%+8 Ri2cpclkdefault $okaypmic@18rockchip,rk805 %Gxin32krk805-clkout2default &$2'>'J'V'bn'cregulatorsDCDC_REG1 zvdd_logic 4 0regulator-state-mem B@DCDC_REG2zvdd_arm 4 0regulator-state-mem ~DCDC_REG3zvcc_ddrregulator-state-memDCDC_REG4zvcc_io2Z2Zregulator-state-mem 2ZLDO_REG1zvcc_18w@w@regulator-state-mem w@LDO_REG2 zvcc18_emmcw@w@regulator-state-mem w@LDO_REG3zvdd_10B@B@regulator-state-mem B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c G&+9 Ri2cpclkdefault ( disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c G'+: Ri2cpclkdefault ) disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi G1+ Rspiclkapb_pclk  txrxdefault *+,-okayspiflash@0jedec,spi-nor(watchdog@ff1a0000 snps,dw-wdt G(pwm@ff1b0000rockchip,rk3328-pwm< Rpwmpclkdefault .: disabledpwm@ff1b0010rockchip,rk3328-pwm< Rpwmpclkdefault /: disabledpwm@ff1b0020rockchip,rk3328-pwm < Rpwmpclkdefault 0: disabledpwm@ff1b0030rockchip,rk3328-pwm0 G2< Rpwmpclkdefault 1: disabledthermal-zonessoc-thermalE[i{2tripstrip-point0ppassivetrip-point1Lpassive3soc-crits criticalcooling-mapsmap030 tsadc@ff250000rockchip,rk3328-tsadc% G:$P$Rtsadcapb_pclkinitdefaultsleep 454B tsadc-apb6)okay?V2efuse@ff260000rockchip,rk3328-efuse&P+> Rpclk_efuseq id@7cpu-leakage@17logic-leakage@19cpu-version@1aBadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( GP%Rsaradcapb_pclkV saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TGZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 Rbuscorefiommu@ff330200rockchip,iommu3 G` h265e_mmu Raclkiface disablediommu@ff340800rockchip,iommu4@ Gb vepu_mmuF Raclkiface disabledvideo-codec@ff350000rockchip,rk3328-vpu5 G vdpuF Raclkhclk78iommu@ff350800rockchip,iommu5@ G vpu_mmuF Raclkiface87iommu@ff360480rockchip,iommu 6@6@ GJ rkvdec_mmuB Raclkiface disabledvop@ff370000rockchip,rk3328-vop7> G x;Raclk_vopdclk_vophclk_vop axiahbdclk9okayport+ endpoint@0:?iommu@ff373f00rockchip,iommu7? G vop_mmu; Raclkifaceokay9hdmi@ff3c0000rockchip,rk3328-dw-hdmi<G#GFRiahbisfrcec;hdmidefault  <=>6okayportsportendpoint?:codec@ff410000rockchip,rk3328-codecA* Rpclkmclk6okayport@0endpoint@ phy@ff430000rockchip,rk3328-hdmi-phyC GSAyRsysclkrefoclkrefpclk hdmi_phyB cpu-versionokay;clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD6x=&'(ABDC"\5H4$zAAA|n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2-phy@100rockchip,rk3328-usb2phyARphyclk usb480m_phy{CokayCotg-port$G;<=otg-bvalidotg-idlinestateokayRhost-port G> linestateokaySdwmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ G  =!JNRbiuciuciu-driveciu-sample),рokay4>Padefault DEFGlHdwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ G  >"KORbiuciuciu-driveciu-sample),р disableddwmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ G ?#LPRbiuciuciu-driveciu-sample),рokay4>xdefault  IJKlethernet@ff540000rockchip,rk3328-gmacT Gmacirq8dWXZYMRstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth6okaydfLLinputrgmiidefault M N 'P$"ethernet@ff550000rockchip,rk3328-gmacU6 Gmacirq8TSSUVIRstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphybdstmmacethmac-phyrmii+O disabledmdiosnps,dwmac-mdio+phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22Vddefault PQ6Ousb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X GMRotgHhostPbq@ R usb2-phyokayusb@ff5c0000 generic-ehci\ G NC RusbhostutmiSusbokayusb@ff5d0000 generic-ohci] G NC RusbhostutmiSusbokayinterrupt-controller@ff811000 arm,gic-400@ @ `  G pinctrlrockchip,rk3328-pinctrl6+@gpio0@ff210000rockchip,gpio-bank! G3_gpio1@ff220000rockchip,gpio-bank" G4Ngpio2@ff230000rockchip,gpio-bank# G5%gpio3@ff240000rockchip,gpio-bank$ G6pcfg-pull-upVpcfg-pull-down^pcfg-pull-noneTpcfg-pull-none-2ma]pcfg-pull-up-2mapcfg-pull-up-4maWpcfg-pull-none-4maZpcfg-pull-down-4mapcfg-pull-none-8maXpcfg-pull-up-8maYpcfg-pull-none-12ma [pcfg-pull-up-12ma \pcfg-output-highpcfg-output-lowpcfg-input-highUpcfg-inputi2c0i2c0-xfer  TT#i2c1i2c1-xfer  TT$i2c2i2c2-xfer   TT(i2c3i2c3-xfer  TT)i2c3-gpio  TThdmi_i2chdmii2c-xfer  TT=pdm-0pdmm0-clk Tpdmm0-fsync Tpdmm0-sdi0 Tpdmm0-sdi1 Tpdmm0-sdi2 Tpdmm0-sdi3 Tpdmm0-clk-sleep Updmm0-sdi0-sleep Updmm0-sdi1-sleep Updmm0-sdi2-sleep Updmm0-sdi3-sleep Updmm0-fsync-sleep Utsadcotp-gpio  T4otp-out  T5uart0uart0-xfer   VTuart0-cts  Tuart0-rts  Tuart0-rts-gpio  Tuart1uart1-xfer  VTuart1-cts T uart1-rts T!uart1-rts-gpio Tuart2-0uart2m0-xfer  VTuart2-1uart2m1-xfer  VT"spi0-0spi0m0-clk Vspi0m0-cs0  Vspi0m0-tx  Vspi0m0-rx  Vspi0m0-cs1  Vspi0-1spi0m1-clk Vspi0m1-cs0 Vspi0m1-tx Vspi0m1-rx Vspi0m1-cs1 Vspi0-2spi0m2-clk V*spi0m2-cs0 V-spi0m2-tx V+spi0m2-rx V,i2s1i2s1-mclk Ti2s1-sclk Ti2s1-lrckrx Ti2s1-lrcktx Ti2s1-sdi Ti2s1-sdo Ti2s1-sdio1 Ti2s1-sdio2 Ti2s1-sdio3 Ti2s1-sleep UUUUUUUUUi2s2-0i2s2m0-mclk Ti2s2m0-sclk Ti2s2m0-lrckrx Ti2s2m0-lrcktx Ti2s2m0-sdi Ti2s2m0-sdo Ti2s2m0-sleep` UUUUUUi2s2-1i2s2m1-mclk Ti2s2m1-sclk Ti2sm1-lrckrx Ti2s2m1-lrcktx Ti2s2m1-sdi Ti2s2m1-sdo Ti2s2m1-sleepP UUUUUspdif-0spdifm0-tx T spdif-1spdifm1-tx Tspdif-2spdifm2-tx Tsdmmc0-0sdmmc0m0-pwren Wsdmmc0m0-gpio Wsdmmc0-1sdmmc0m1-pwren Wsdmmc0m1-gpio W`sdmmc0sdmmc0-clk XDsdmmc0-cmd YEsdmmc0-dectn WFsdmmc0-wrprt Wsdmmc0-bus1 Ysdmmc0-bus4@ YYYYGsdmmc0-gpio WWWWWWWWsdmmc0extsdmmc0ext-clk Zsdmmc0ext-cmd Wsdmmc0ext-wrprt Wsdmmc0ext-dectn Wsdmmc0ext-bus1 Wsdmmc0ext-bus4@ WWWWsdmmc0ext-gpio WWWWWWWWsdmmc1sdmmc1-clk  Xsdmmc1-cmd  Ysdmmc1-pwren Ysdmmc1-wrprt Ysdmmc1-dectn Ysdmmc1-bus1 Ysdmmc1-bus4@ YYYYsdmmc1-gpio  W WWWWWWWWemmcemmc-clk [Iemmc-cmd \Jemmc-pwren Temmc-rstnout Temmc-bus1 \emmc-bus4@ \\\\emmc-bus8 \\\\\\\\Kpwm0pwm0-pin T.pwm1pwm1-pin T/pwm2pwm2-pin T0pwmirpwmir-pin T1gmac-1rgmiim1-pins`  X ZZXZZZ Z ZX XZZXXX XZXXXXMrmiim1-pins ][]]]] ] ][ [ T TTTTTgmac2phyfephyled-speed100 Tfephyled-speed10 Tfephyled-duplex Tfephyled-rxm0 Tfephyled-txm0 Tfephyled-linkm0 Tfephyled-rxm1 TPfephyled-txm1 Tfephyled-linkm1 TQtsadc_pintsadc-int  Ttsadc-gpio  Thdmi_pinhdmi-cec T<hdmi-hpd ^>cif-0dvp-d2d9-m0 TTTTT T T TTTTTcif-1dvp-d2d9-m1 TTTTTTTTTTTTirir-int Tbpmicpmic-int-l V&usb2usb20-host-drv Tachosenserial2:1500000n8external-gmac-clock fixed-clocksY@ gmac_clkinLsdmmc-regulatorregulator-fixed _default `zvcc_sd2Z2Z&Hvcc-host-5v-regulatorregulator-fixed _default a zvcc_host_5v&'vcc-host1-5v-regulatorregulator-fixed _default a zvcc_host1_5v&'vcc-sysregulator-fixedzvcc_sysLK@LK@'ir-receivergpio-ir-receiver 1% bdefaultleds gpio-ledspower 1c7mmc0standby 1c 7heartbeatsoundaudio-graph-cardMrockchip,rk3328Sdespdif-ditlinux,spdif-ditportendpointf compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellsdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsclock-names#dma-cellsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellsstatusdai-formatmclk-fsremote-endpointpinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltspi-max-frequency#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplymmc-hs200-1_8vnon-removablevqmmc-supplyclock_in_outphy-supplyphy-modesnps,force_thresh_dma_modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dma#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplygpioslinux,default-triggerlabeldais