o8( rockchip,px30-evbrockchip,px30 +7Rockchip PX30 EVBaliases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000/serial@ff178000/spi@ff1d0000/spi@ff1d8000cpus+cpu@0cpuarm,cortex-a35psciZcpu@1cpuarm,cortex-a35psciZcpu@2cpuarm,cortex-a35psciZcpu@3cpuarm,cortex-a35psciZ idle-statespscicpu-sleeparm,idle-state-DxUecluster-sleeparm,idle-state-DUecpu0-opp-tableoperating-points-v2vopp-408000000Q ~~p@opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem okayfirmwareopteelinaro,optee-tzsmcexternal-gmac-clock fixed-clock gmac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24mxin32k fixed-clockxin32kpower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+Opd_usb@5<" pd_sdcard@7;"pd_gmac@9  C@?"pd_mmc_nand@10 @978:"pd_vpu@11 K"pd_vo@12 XD56"pd_vi@13 (3"pd_gpu@14I"syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+^io-domains$rockchip,px30-pmu-io-voltage-domainokayreboot-modesyscon-reboot-mode)0RB@RB NRBZRBfRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart   tbaudclkapb_pclk!!txrxdefault "#$ disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  ti2s_clki2s_hclk!!txrxdefault%&'(okayi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s ti2s_clki2s_hclk!!txrxdefault)*+, disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+Nio-domains rockchip,px30-io-voltage-domainokayserial@ff158000$rockchip,px30-uartsnps,dw-apb-uart Itbaudclkapb_pclk!!txrxdefault-.okayserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart Jtbaudclkapb_pclk!!txrxdefault/okayserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart Ktbaudclkapb_pclk!!txrxdefault 012 disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart Ltbaudclkapb_pclk!! txrxdefault 345 disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart Mtbaudclkapb_pclk! ! txrxdefault 678 disabledi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN ti2cpclk default9+okayi2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO ti2cpclk default:+ disabledi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP ti2cpclk  default;+ disabledi2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q ti2cpclk  default<+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $Utspiclkapb_pclk! ! txrxdefault=>?@+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %Vtspiclkapb_pclk!!txrxdefaultABCDE+ disabledwatchdog@ff1e0000 snps,dw-wdt[ % disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S tpwmpclkdefaultF disabledpwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S tpwmpclkdefaultGokaykpwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S tpwmpclkdefaultH disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S tpwmpclkdefaultI disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T tpwmpclkdefaultJ disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T tpwmpclkdefaultK disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T tpwmpclkdefaultL disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T tpwmpclkdefaultM disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& tpclktimeramba simple-bus+dmac@ff240000arm,pl330arm,primecell$@ tapb_pclk!saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-Wtsaradcapb_pclk$ +saradc-apbokayjclock-controller@ff2b0000rockchip,px30-cru+7NDQaFqclock-controller@ff2bc000rockchip,px30-pmucru+7NDPQ   @I(aG#F рр  usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >totgvotg~@ Ookayusb@ff340000 generic-ehci4 <tusbhostOokayusb@ff350000 generic-ohci5 =tusbhostOokayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[tstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed7NrmiidefaultPQO $^ +stmmacethokayoutputR S  PPdwmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CDtbiuciuciu-driveciu-sample2=рdefaultTUVWOokayKUgx dwmmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EFtbiuciuciu-driveciu-sample2=рdefault XYZO okayKg[dwmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GHtbiuciuciu-driveciu-sample2=рO okayKUvop@ff460000rockchip,px30-vop-bigF Mtaclk_vopdclk_vophclk_vop$345 +axiahbdclk\O 7Nokayport+ iommu@ff460f00rockchip,iommuF M vopb_mmu taclkhclkO okay\vop@ff470000rockchip,px30-vop-litG Ntaclk_vopdclk_vophclk_vop$789 +axiahbdclk]O 7Nokayport+ iommu@ff470f00rockchip,iommuG O vopl_mmu taclkhclkO okay]qos@ff518000sysconQ qos@ff520000sysconR qos@ff52c000sysconR qos@ff538000sysconS qos@ff538080sysconS qos@ff538100sysconS qos@ff538180sysconS qos@ff540000sysconT  qos@ff540080sysconT  qos@ff548000sysconT qos@ff548080sysconT qos@ff548100sysconT qos@ff548180sysconT qos@ff548200sysconT qos@ff550000sysconU qos@ff550080sysconU qos@ff550100sysconU qos@ff550180sysconU qos@ff558000sysconU qos@ff558080sysconU pinctrlrockchip,px30-pinctrl7N^+gpio0@ff040000rockchip,gpio-bank  .mgpio1@ff250000rockchip,gpio-bank% \.gpio2@ff260000rockchip,gpio-bank& ].Sgpio3@ff270000rockchip,gpio-bank' ^.pcfg-pull-up:apcfg-pull-downGhpcfg-pull-noneV`pcfg-pull-none-2maVcpcfg-pull-up-2ma:cpcfg-pull-up-4ma:cbpcfg-pull-none-4maVcpcfg-pull-down-4maGcpcfg-pull-none-8maVcepcfg-pull-up-8ma:ccpcfg-pull-none-12maVc gpcfg-pull-up-12ma:c fpcfg-pull-none-smtVr_pcfg-output-highpcfg-output-lowipcfg-input-high:dpcfg-inputi2c0i2c0-xfer _ _9i2c1i2c1-xfer __:i2c2i2c2-xfer __;i2c3i2c3-xfer  _ _<tsadctsadc-otp-gpio`tsadc-otp-out`uart0uart0-xfer  a a"uart0-cts `#uart0-rts `$uart0-rts-gpio `uart1uart1-xfer aa-uart1-cts`.uart1-rts`uart1-rts-gpio`uart2-m0uart2m0-xfer aa/uart2-m1uart2m1-xfer  aauart3-m0uart3m0-xfer aauart3m0-cts`uart3m0-rts`uart3m0-rts-gpio`uart3-m1uart3m1-xfer aa0uart3m1-cts `1uart3m1-rts `2uart3m1-rts-gpio `uart4uart4-xfer aa3uart4-cts`4uart4-rts`5uart5uart5-xfer aa6uart5-cts`7uart5-rts`8spi0spi0-clkb=spi0-csnb>spi0-miso b?spi0-mosi b@spi0-clk-hscspi0-miso-hs cspi0-mosi-hs cspi1spi1-clkbAspi1-csn0 bBspi1-csn1 bCspi1-misobDspi1-mosi bEspi1-clk-hscspi1-miso-hscspi1-mosi-hs cpdmpdm-clk0m0`pdm-clk0m1`pdm-clk1`pdm-sdi0m0`pdm-sdi0m1`pdm-sdi1`pdm-sdi2`pdm-sdi3`pdm-clk0m0-sleepdpdm-clk0m1-sleepdpdm-clk1-sleepdpdm-sdi0m0-sleepdpdm-sdi0m1-sleepdpdm-sdi1-sleepdpdm-sdi2-sleepdpdm-sdi3-sleepdi2s0i2s0-8ch-mclk`i2s0-8ch-sclktx`i2s0-8ch-sclkrx `i2s0-8ch-lrcktx`i2s0-8ch-lrckrx `i2s0-8ch-sdo0`i2s0-8ch-sdo1`i2s0-8ch-sdo2`i2s0-8ch-sdo3`i2s0-8ch-sdi0`i2s0-8ch-sdi1 `i2s0-8ch-sdi2 `i2s0-8ch-sdi3`i2s1i2s1-2ch-mclk`i2s1-2ch-sclk`%i2s1-2ch-lrck`&i2s1-2ch-sdi`'i2s1-2ch-sdo`(i2s2i2s2-2ch-mclk`i2s2-2ch-sclk`)i2s2-2ch-lrck`*i2s2-2ch-sdi`+i2s2-2ch-sdo`,sdmmcsdmmc-clkeTsdmmc-cmdcUsdmmc-detcVsdmmc-bus1csdmmc-bus4@ccccWsdmmc-gpio`bbbbbbsdiosdio-clk`Zsdio-cmdaYsdio-bus4@aaaaXsdio-gpio`aaaaaaemmcemmc-clk eemmc-cmd cemmc-pwren`emmc-rstnout `emmc-bus1cemmc-bus4@ccccemmc-bus8ccccccccflashflash-cs0`flash-rdy `flash-dqs `flash-ale `flash-cle `flash-wrn `flash-csl`flash-rdn`flash-bus8fffffffflcdclcdc-rgb-dclk-pinglcdc-rgb-m0-hsync-pinglcdc-rgb-m0-vsync-pinglcdc-rgb-m0-den-pinglcdc-rgb888-m0-data-pinseeee e e eeee e eeeeeeeeeeeeelcdc-rgb666-m0-data-pins eeee e e eeee e eeeeeeelcdc-rgb565-m0-data-pinseeee e e eeee e eeeeelcdc-rgb888-m1-data-pinsee e e eeeeeeeeeeeeelcdc-rgb666-m1-data-pinsee e e eeeeeeelcdc-rgb565-m1-data-pinsee e e eeeeepwm0pwm0-pin`Fpwm1pwm1-pin`Gpwm2pwm2-pin `Hpwm3pwm3-pin`Ipwm4pwm4-pin`Jpwm5pwm5-pin`Kpwm6pwm6-pin`Lpwm7pwm7-pin`Mgmacrmii-pinsggg````` `Pmac-refclk-12ma gQmac-refclk `cif-m0cif-clkout-m0 `dvp-d2d9-m0````````` ` ` `dvp-d0d1-m0  ``d10-d11-m0 ``cif-m1cif-clkout-m1`dvp-d2d9-m1```` ` ```````dvp-d0d1-m1 ``d10-d11-m1 ``ispisp-prelight`headphonehp-dethpmicpmic_intasoc_slppin_gpioisoc_slppin_slp`soc_slppin_rst`sdio-pwrseqwifi-enable-h`lchosenserial2:1500000n8adc-keys adc-keysjbuttonsw@desc-key esc0home-key homef menu-key menuxvol-down-key  volume downrvol-up-key  volume upsBhbacklightpwm-backlight5kasdio-pwrseqmmc-pwrseq-simpledefaultl :m[vcc-phy-regulatorregulator-fixedFvcc_phyUiRvccsysregulator-fixed Fvcc5v0_sysUi{LK@LK@ compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2phandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cells#power-domain-cellspm_qosoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0#sound-dai-cells#interrupt-cellsinterrupt-controller#pwm-cellsranges#dma-cells#io-channel-cellsresetsreset-namesrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmapower-domainsinterrupt-namesphy-modeclock_in_outphy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104keep-power-in-suspendnon-removablemmc-pwrseqmmc-hs200-1_8viommus#iommu-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltpwmsreset-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvolt