98( H ',Qualcomm Technologies, Inc. SDM845 MTP2qcom,sdm845-mtpaliases!=/soc@0/geniqup@8c0000/i2c@880000!B/soc@0/geniqup@8c0000/i2c@884000!G/soc@0/geniqup@8c0000/i2c@888000!L/soc@0/geniqup@8c0000/i2c@88c000!Q/soc@0/geniqup@8c0000/i2c@890000!V/soc@0/geniqup@8c0000/i2c@894000![/soc@0/geniqup@8c0000/i2c@898000!`/soc@0/geniqup@8c0000/i2c@89c000!e/soc@0/geniqup@ac0000/i2c@a80000!j/soc@0/geniqup@ac0000/i2c@a84000!o/soc@0/geniqup@ac0000/i2c@a88000!u/soc@0/geniqup@ac0000/i2c@a8c000!{/soc@0/geniqup@ac0000/i2c@a90000!/soc@0/geniqup@ac0000/i2c@a94000!/soc@0/geniqup@ac0000/i2c@a98000!/soc@0/geniqup@ac0000/i2c@a9c000!/soc@0/geniqup@8c0000/spi@880000!/soc@0/geniqup@8c0000/spi@884000!/soc@0/geniqup@8c0000/spi@888000!/soc@0/geniqup@8c0000/spi@88c000!/soc@0/geniqup@8c0000/spi@890000!/soc@0/geniqup@8c0000/spi@894000!/soc@0/geniqup@8c0000/spi@898000!/soc@0/geniqup@8c0000/spi@89c000!/soc@0/geniqup@ac0000/spi@a80000!/soc@0/geniqup@ac0000/spi@a84000!/soc@0/geniqup@ac0000/spi@a88000!/soc@0/geniqup@ac0000/spi@a8c000!/soc@0/geniqup@ac0000/spi@a90000!/soc@0/geniqup@ac0000/spi@a94000!/soc@0/geniqup@ac0000/spi@a98000!/soc@0/geniqup@ac0000/spi@a9c000$/soc@0/geniqup@ac0000/serial@a84000chosenserial0:115200n8memory@80000000memory reserved-memory  memory@85700000 p`memory@85e00000 memory@85fc0000 memory@85fe0000 2qcom,cmd-db memory@86000000 #memory@86200000 memory@88f000002qcom,rmtfs-mem #2memory@8ab00000 @memory@8bf00000 Pmemory@8c400000 @memory@8c410000 APmemory@8c415000 AP memory@8c500000 Pmemory@8df00000 memory@8e000000 cmemory@95800000 Pmemory@95d00000  memory@96500000 P bmemory@96700000 p@memory@97b00000 cpus cpu@0cpu 2qcom,kryo385 KI [xo_boardsleep-clk 2fixed-clock>Kfirmwarescm2qcom,scm-sdm845qcom,scmremoteproc-adsp2qcom,sdm845-adsp-pas@n#wdogfatalreadyhandoverstop-ackxostopokayglink-edge 3lpassfastrpc 2qcom,fastrpcfastrpcglink-apps-dspadsp compute-cb@32qcom,fastrpc-compute-cb  #compute-cb@42qcom,fastrpc-compute-cb  $remoteproc-cdsp2qcom,sdm845-cdsp-pas@nB#wdogfatalreadyhandoverstop-ackxo !stopokayglink-edge 3>turingfastrpc 2qcom,fastrpcfastrpcglink-apps-dspcdsp compute-cb@12qcom,fastrpc-compute-cb  0compute-cb@22qcom,fastrpc-compute-cb  0compute-cb@32qcom,fastrpc-compute-cb  0compute-cb@42qcom,fastrpc-compute-cb  0compute-cb@52qcom,fastrpc-compute-cb  0compute-cb@62qcom,fastrpc-compute-cb  0compute-cb@72qcom,fastrpc-compute-cb  0compute-cb@82qcom,fastrpc-compute-cb  0hwlock2qcom,tcsr-mutex " $smem 2qcom,smem#.$smp2p-cdsp 2qcom,smp2p6^ 3@@master-kernelOmaster-kernel_!slave-kernel Oslave-kernelvsmp2p-lpass 2qcom,smp2p6 3 @master-kernelOmaster-kernel_slave-kernel Oslave-kernelvsmp2p-mpss 2qcom,smp2p6 3@master-kernelOmaster-kernel_]slave-kernel Oslave-kernelv\smp2p-slpi 2qcom,smp2p6 3@master-kernelOmaster-kernel_slave-kernel Oslave-kernelvpsci 2arm,psci-1.0Csmcsoc@0   2simple-busclock-controller@1000002qcom,gcc-sdm845 >%qfprom@784000 2qcom,qfprom x@ hstx-trim-primary@1eb hstx-trim-secondary@1eb rng@793000 2qcom,prng-ee y0%@coregeniqup@8c00002qcom,geni-se-qup ` m-ahbs-ahb%d%e   disabledi2c@8800002qcom,geni-i2c @se%Ddefault& 3Y  disabledspi@8800002qcom,geni-spi @se%Ddefault' 3Y  disabledserial@8800002qcom,geni-uart @se%Ddefault( 3Y disabledi2c@8840002qcom,geni-i2c @@se%Fdefault) 3Z  disabledspi@8840002qcom,geni-spi @@se%Fdefault* 3Z  disabledserial@8840002qcom,geni-uart @@se%Fdefault+ 3Z disabledi2c@8880002qcom,geni-i2c @se%Hdefault, 3[  disabledspi@8880002qcom,geni-spi @se%Hdefault- 3[  disabledserial@8880002qcom,geni-uart @se%Hdefault. 3[ disabledi2c@88c0002qcom,geni-i2c @se%Jdefault/ 3\  disabledspi@88c0002qcom,geni-spi @se%Jdefault0 3\  disabledserial@88c0002qcom,geni-uart @se%Jdefault1 3\ disabledi2c@8900002qcom,geni-i2c @se%Ldefault2 3]  disabledspi@8900002qcom,geni-spi @se%Ldefault3 3]  disabledserial@8900002qcom,geni-uart @se%Ldefault4 3] disabledi2c@8940002qcom,geni-i2c @@se%Ndefault5 3^  disabledspi@8940002qcom,geni-spi @@se%Ndefault6 3^  disabledserial@8940002qcom,geni-uart @@se%Ndefault7 3^ disabledi2c@8980002qcom,geni-i2c @se%Pdefault8 3_  disabledspi@8980002qcom,geni-spi @se%Pdefault9 3_  disabledserial@8980002qcom,geni-uart @se%Pdefault: 3_ disabledi2c@89c0002qcom,geni-i2c @se%Rdefault; 3`  disabledspi@89c0002qcom,geni-spi @se%Rdefault< 3`  disabledserial@89c0002qcom,geni-uart @se%Rdefault= 3` disabledgeniqup@ac00002qcom,geni-se-qup ` m-ahbs-ahb%f%g  okayi2c@a800002qcom,geni-i2c @se%Tdefault> 3a  disabledspi@a800002qcom,geni-spi @se%Tdefault? 3a  disabledserial@a800002qcom,geni-uart @se%Tdefault@ 3a disabledi2c@a840002qcom,geni-i2c @@se%VdefaultA 3b  disabledspi@a840002qcom,geni-spi @@se%VdefaultB 3b  disabledserial@a840002qcom,geni-debug-uart @@se%VdefaultC 3bokayi2c@a880002qcom,geni-i2c @se%XdefaultD 3c okayKspi@a880002qcom,geni-spi @se%XdefaultE 3c  disabledserial@a880002qcom,geni-uart @se%XdefaultF 3c disabledi2c@a8c0002qcom,geni-i2c @se%ZdefaultG 3d  disabledspi@a8c0002qcom,geni-spi @se%ZdefaultH 3d  disabledserial@a8c0002qcom,geni-uart @se%ZdefaultI 3d disabledi2c@a900002qcom,geni-i2c @se%\defaultJ 3e  disabledspi@a900002qcom,geni-spi @se%\defaultK 3e  disabledserial@a900002qcom,geni-uart @se%\defaultL 3e disabledi2c@a940002qcom,geni-i2c @@se%^defaultM 3f  disabledspi@a940002qcom,geni-spi @@se%^defaultN 3f  disabledserial@a940002qcom,geni-uart @@se%^defaultO 3f disabledi2c@a980002qcom,geni-i2c @se%`defaultP 3g  disabledspi@a980002qcom,geni-spi @se%`defaultQ 3g  disabledserial@a980002qcom,geni-uart @se%`defaultR 3g disabledi2c@a9c0002qcom,geni-i2c @se%bdefaultS 3h  disabledspi@a9c0002qcom,geni-spi @se%bdefaultT 3h  disabledserial@a9c0002qcom,geni-uart @se%bdefaultU 3h disabledcache-controller@11000002qcom,sdm845-llcc   0llcc_basellcc_broadcast_base 3Fufshc@1d84000+2qcom,sdm845-ufshcqcom,ufshcjedec,ufs-2.0 @% 3 Vufsphy#% ncore_clkbus_aggr_clkiface_clkcore_clk_uniproref_clktx_lane0_sync_clkrx_lane0_sync_clkrx_lane1_sync_clk@%%%%%%%@1 <4`рokay ?WKXV 'Yphy@1d870002qcom,sdm845-qmp-ufs-phy p   refref_aux%%gYnufsphyokayzZ[lanes@1d87400P tv|xzVsyscon@1f400002syscon "pinctrl@34000002qcom,sdm845-pinctrl @ 3vWQWqspi-clkpinmuxgpio95 qspi_clkqspi-cs0pinmuxgpio90qspi_csqspi-cs1pinmuxgpio89qspi_csqspi-data01pinmux-datagpio91gpio92 qspi_dataqspi-data12pinmux-datagpio93gpio94 qspi_dataqup-i2c0-default&pinmux gpio0gpio1qup0qup-i2c1-default)pinmuxgpio17gpio18qup1qup-i2c2-default,pinmuxgpio27gpio28qup2qup-i2c3-default/pinmuxgpio41gpio42qup3qup-i2c4-default2pinmuxgpio89gpio90qup4qup-i2c5-default5pinmuxgpio85gpio86qup5qup-i2c6-default8pinmuxgpio45gpio46qup6qup-i2c7-default;pinmuxgpio93gpio94qup7qup-i2c8-default>pinmuxgpio65gpio66qup8qup-i2c9-defaultApinmux gpio6gpio7qup9qup-i2c10-defaultDpinmuxgpio55gpio56qup10pinconfgpio55gpio56qup-i2c11-defaultGpinmuxgpio31gpio32qup11qup-i2c12-defaultJpinmuxgpio49gpio50qup12qup-i2c13-defaultMpinmuxgpio105gpio106qup13qup-i2c14-defaultPpinmuxgpio33gpio34qup14qup-i2c15-defaultSpinmuxgpio81gpio82qup15qup-spi0-default'pinmuxgpio0gpio1gpio2gpio3qup0qup-spi1-default*pinmuxgpio17gpio18gpio19gpio20qup1qup-spi2-default-pinmuxgpio27gpio28gpio29gpio30qup2qup-spi3-default0pinmuxgpio41gpio42gpio43gpio44qup3qup-spi4-default3pinmuxgpio89gpio90gpio91gpio92qup4qup-spi5-default6pinmuxgpio85gpio86gpio87gpio88qup5qup-spi6-default9pinmuxgpio45gpio46gpio47gpio48qup6qup-spi7-default<pinmuxgpio93gpio94gpio95gpio96qup7qup-spi8-default?pinmuxgpio65gpio66gpio67gpio68qup8qup-spi9-defaultBpinmuxgpio6gpio7gpio4gpio5qup9qup-spi10-defaultEpinmuxgpio55gpio56gpio53gpio54qup10qup-spi11-defaultHpinmuxgpio31gpio32gpio33gpio34qup11qup-spi12-defaultKpinmuxgpio49gpio50gpio51gpio52qup12qup-spi13-defaultNpinmux gpio105gpio106gpio107gpio108qup13qup-spi14-defaultQpinmuxgpio33gpio34gpio31gpio32qup14qup-spi15-defaultTpinmuxgpio81gpio82gpio83gpio84qup15qup-uart0-default(pinmux gpio2gpio3qup0qup-uart1-default+pinmuxgpio19gpio20qup1qup-uart2-default.pinmuxgpio29gpio30qup2qup-uart3-default1pinmuxgpio43gpio44qup3qup-uart4-default4pinmuxgpio91gpio92qup4qup-uart5-default7pinmuxgpio87gpio88qup5qup-uart6-default:pinmuxgpio47gpio48qup6qup-uart7-default=pinmuxgpio95gpio96qup7qup-uart8-default@pinmuxgpio67gpio68qup8qup-uart9-defaultCpinmux gpio4gpio5qup9pinconf-txgpio4pinconf-rxgpio5 qup-uart10-defaultFpinmuxgpio53gpio54qup10qup-uart11-defaultIpinmuxgpio33gpio34qup11qup-uart12-defaultLpinmuxgpio51gpio52qup12qup-uart13-defaultOpinmuxgpio107gpio108qup13qup-uart14-defaultRpinmuxgpio31gpio32qup14qup-uart15-defaultUpinmuxgpio83gpio84qup15sdc2-clkpinconf sdc2_clksdc2-cmdpinconf sdc2_cmd sdc2-datapinconf sdc2_data sd-card-det-npinmuxgpio126gpiopinconfgpio126 remoteproc@40800002qcom,sdm845-mss-pil  H qdsp6rmbLn \\\\\0wdogfatalreadyhandoverstop-ackshutdown-ack@%$%'%%%%(%&%@2ifacebusmemgpll0_msssnoc_aximnoc_axiprngxo]stopg^_ nmss_restartpdc_reset"0P@ #`aaa(load_statecxmxmssmbabmpsscglink-edge 3modem clock-controller@50900002qcom,sdm845-gpucc  >xostm@6002000 2arm,coresight-stmarm,primecell   (stm-basestm-stimulus-base` apb_pclkout-portsportendpoint;dffunnel@6041000+2arm,coresight-dynamic-funnelarm,primecell ` apb_pclkout-portsportendpoint;ejin-ports port@7 endpoint;fdfunnel@6043000+2arm,coresight-dynamic-funnelarm,primecell 0` apb_pclkout-portsportendpoint;gkin-ports port@5 endpoint;hfunnel@6045000+2arm,coresight-dynamic-funnelarm,primecell P` apb_pclkout-portsportendpoint;ioin-ports port@0 endpoint;jeport@2 endpoint;kgreplicator@6046000/2arm,coresight-dynamic-replicatorarm,primecell `` apb_pclkout-portsportendpoint;lpin-portsportendpoint;mnetf@6047000 2arm,coresight-tmcarm,primecell p` apb_pclkout-portsportendpoint;nmin-ports port@1 endpoint;oietr@6048000 2arm,coresight-tmcarm,primecell ` apb_pclkKin-portsportendpoint;pletm@7040000"2arm,coresight-etm4xarm,primecell ` apb_pclkout-portsportendpoint;qzetm@7140000"2arm,coresight-etm4xarm,primecell ` apb_pclkout-portsportendpoint;r{etm@7240000"2arm,coresight-etm4xarm,primecell $` apb_pclkout-portsportendpoint;s|etm@7340000"2arm,coresight-etm4xarm,primecell 4` apb_pclkout-portsportendpoint;t}etm@7440000"2arm,coresight-etm4xarm,primecell D` apb_pclkout-portsportendpoint;u~etm@7540000"2arm,coresight-etm4xarm,primecell T` apb_pclkout-portsportendpoint;vetm@7640000"2arm,coresight-etm4xarm,primecell d` apb_pclkout-portsportendpoint;wetm@7740000"2arm,coresight-etm4xarm,primecell t` apb_pclkout-portsportendpoint;xfunnel@7800000+2arm,coresight-dynamic-funnelarm,primecell ` apb_pclkout-portsportendpoint;yin-ports port@0 endpoint;zqport@1 endpoint;{rport@2 endpoint;|sport@3 endpoint;}tport@4 endpoint;~uport@5 endpoint;vport@6 endpoint;wport@7 endpoint;xfunnel@7810000+2arm,coresight-dynamic-funnelarm,primecell ` apb_pclkout-portsportendpoint;hin-portsportendpoint;ysdhci@8804000$2qcom,sdm845-sdhciqcom,sdhci-msm-v5 @3hc_irqpwr_irq%h%i ifacecore okaydefault^j wW~spi@88df0002qcom,sdm845-qspiqcom,qspi-v1   3R%% ifacecore disabledphy@88e20002qcom,sdm845-qusb2-phy  okay% cfg_ahbrefg%Zphy@88e30002qcom,sdm845-qusb2-phy 0okay% cfg_ahbrefg% Zphy@88e90002qcom,sdm845-qmp-usb3-phy  reg-basedp_comokay>   %%%%auxcfg_ahbrefcom_auxg%% nphycommonz[Zlanes@88e9200` ((%pipe0[usb3_phy_pipe_clk_srcphy@88eb0002qcom,sdm845-qmp-usb3-uni-phy okay>   %%%%auxcfg_ahbrefcom_auxg%% nphycommonz[Zlane@88eb200@ (p%pipe0[usb3_uni_phy_pipe_clk_srcusb@a6f88002qcom,sdm845-dwc3qcom,dwc3 ookay  (% %%%%#cfg_noccoreifacemock_utmisleep %%$р032hs_phy_irqss_phy_irqdm_hs_phy_irqdp_hs_phy_irq#%g%dwc3@a600000 2snps,dwc3 ` 3 @.Gusb2-phyusb3-phy _peripheralusb@a8f88002qcom,sdm845-dwc3qcom,dwc3 okay  (% %%%%#cfg_noccoreifacemock_utmisleep %%$р032hs_phy_irqss_phy_irqdm_hs_phy_irqdp_hs_phy_irq#%g%dwc3@a800000 2snps,dwc3  3 `.Gusb2-phyusb3-phy _peripheralvideo-codec@aa000002qcom,sdm845-venus  3#  coreifacebusvideo-core02venus-decoder corebus#video-core12venus-encoder corebus#clock-controller@ab000002qcom,sdm845-videocc >mdss@ae000002qcom,sdm845-mdss mdss#%% ifacebuscore  3Sv  disabled  mdp@ae010002qcom,sdm845-dpu    mdpvbif  ifacebuscorevsync $3 disabledports port@0 endpoint;port@1 endpoint;dsi@ae940002qcom,mdss-dsi-ctrl @ dsi_ctrl30$bytebyte_intfpixelcoreifacebusdsi disabledports port@0 endpoint;port@1 endpointdsi-phy@ae944002qcom,dsi-phy-10nm0 D F Jdsi_phydsi_phy_lanedsi_pll> ifaceref disableddsi@ae960002qcom,mdss-dsi-ctrl ` dsi_ctrl30 $bytebyte_intfpixelcoreifacebusdsi disabledports port@0 endpoint;port@1 endpointdsi-phy@ae964002qcom,dsi-phy-10nm0 d f jdsi_phydsi_phy_lanedsi_pll> ifaceref disabledgpu@50000002qcom,adreno-630.2qcom,adrenog   kgsl_3d0_reg_memorycx_mem 3,xzap-shaderopp-table2operating-points-v2opp-710000000*Qopp-675000000(;opp-596000000#=@opp-520000000opp-414000000#opp-342000000bopp-257000000Q@@iommu@5040000!2qcom,sdm845-smmu-v2qcom,smmu-v2 x3lmnopqrs%!% busiface#gmu@506a000&2qcom,adreno-gmu-630.2qcom,adreno-gmu0  ( Hgmugmu_pdcgmu_pdc_seq301hfigmu %%!gmucxoaximemnoc#(cxgxxopp-table2operating-points-v2opp-400000000ׄopp-200000000 0clock-controller@af000002qcom,sdm845-dispcc >reset-controller@b2e00002qcom,sdm845-pdc-global ._thermal-sensor@c263000 2qcom,sdm845-tsensqcom,tsens-v2  &0 "  thermal-sensor@c265000 2qcom,sdm845-tsensqcom,tsens-v2  &P "0reset-controller@c2a00002qcom,sdm845-aoss-cc *^qmp@c3000002qcom,sdm845-aoss-qmp 0 3>`cxebispmi@c4400002qcom,spmi-pmic-arbP D ``p @`corechnlsobsrvrintrcnfg periph_irq 3 viommu@15000000!2qcom,sdm845-smmu-500arm,mmu-500  3A`abcdefghijklmnopqrstuv;<=>?@ABCDEFGHIJKLMNOPQRSTUVWclock-controller@170140002qcom,sdm845-lpasscc  @0 ccqdsp6ss> disabledmailbox@179900002qcom,sdm845-apss-shared  rsc@179c0000 apps_rsc2qcom,rpmh-rsc0 drv-0drv-1drv-2$3 & 2clock-controller2qcom,sdm845-rpmh-clk>xopower-controller2qcom,sdm845-rpmhpdxaopp-table2operating-points-v2opp1opp20opp3@opp4opp5opp6opp7@opp8Popp9opp10interconnect2qcom,sdm845-rsc-hlosBpm8998-rpmh-regulators2qcom,pm8998-rpmh-regulatorsVacq/DVgu  smps2 & >smps3 &@ >@smps5 &  > smps7 &  >ldo1 & m > m VZldo2 &O >O V mldo3 &B@ >B@ Vldo5 & 5 > 5 Vldo6 &R >R Vldo7 &w@ >w@ Vldo8 &O >  Vldo9 &@ >, Vldo10 &@ >, Vldo11 &B@ > Vldo12 &w@ >w@ Vldo13 &w@ >-* Vldo14 &w@ >w@ Vldo15 &w@ >w@ Vldo16 &)B >)B Vldo17 & > Vldo18 &)B >-* Vldo19 &+@ >/] Vldo20 &)B >-* VXldo21 &)B >-* Vldo22 &+ >2 Vldo23 &- >2 Vldo24 &/ >/ Vldo25 &2Z >2 Vldo26 &O >O V[ldo28 &+@ >- Vlvs1 &w@ >w@lvs2 &w@ >w@pmi8998-rpmh-regulators2qcom,pmi8998-rpmh-regulatorsVb bob &2 >6 V pm8005-rpmh-regulators2qcom,pm8005-rpmh-regulatorsVccqsmps3 & ' > 'interrupt-controller@17a00000 2arm,gic-v3  v   3 gic-its@17a400002arm,gic-v3-its    disabledtimer@17c90000  2arm,armv7-timer-mem frame@17ca0000 3  frame@17cc0000  3  disabledframe@17cd0000  3   disabledframe@17ce0000  3   disabledframe@17cf0000  3   disabledframe@17d00000  3   disabledframe@17d10000  3   disabledcpufreq@17d430002qcom,cpufreq-hw  0Xfreq-domain0freq-domain1% xoalternate wifi@188000002qcom,wcn3990-wifiokay membasecxo_ref_clk_pin3 @    thermal-zonescpu0-thermal . D Rtripstrip-point0 b_ npassivetrip-point1 bs npassivecpu_crit b n criticalcooling-mapsmap0 y0 ~map1 y0 ~cpu1-thermal . D Rtripstrip-point0 b_ npassivetrip-point1 bs npassivecpu_crit b n criticalcooling-mapsmap0 y0 ~map1 y0 ~cpu2-thermal . D Rtripstrip-point0 b_ npassivetrip-point1 bs npassivecpu_crit b n criticalcooling-mapsmap0 y0 ~map1 y0 ~cpu3-thermal . D Rtripstrip-point0 b_ npassivetrip-point1 bs npassivecpu_crit b n criticalcooling-mapsmap0 y0 ~map1 y0 ~cpu4-thermal . D Rtripstrip-point0 b_ npassivetrip-point1 bs npassivecpu_crit b n criticalcooling-mapsmap0 y0 ~map1 y0 ~cpu5-thermal . D Rtripstrip-point0 b_ npassivetrip-point1 bs npassivecpu_crit b n criticalcooling-mapsmap0 y0 ~map1 y0 ~cpu6-thermal . D R tripstrip-point0 b_ npassivetrip-point1 bs npassivecpu_crit b n criticalcooling-mapsmap0 y0 ~map1 y0 ~cpu7-thermal . D R tripstrip-point0 b_ npassivetrip-point1 bs npassivecpu_crit b n criticalcooling-mapsmap0 y0 ~map1 y0 ~aoss0-thermal . D Rtripstrip-point0 b_ nhotcluster0-thermal . D Rtripstrip-point0 b_ nhotcluster0_crit b n criticalcluster1-thermal . D Rtripstrip-point0 b_ nhotcluster1_crit b n criticalgpu-thermal-top . D R tripstrip-point0 b_ nhotgpu-thermal-bottom . D R tripstrip-point0 b_ nhotaoss1-thermal . D Rtripstrip-point0 b_ nhotq6-modem-thermal . D Rtripstrip-point0 b_ nhotmem-thermal . D Rtripstrip-point0 b_ nhotwlan-thermal . D Rtripstrip-point0 b_ nhotq6-hvx-thermal . D Rtripstrip-point0 b_ nhotcamera-thermal . D Rtripstrip-point0 b_ nhotvideo-thermal . D Rtripstrip-point0 b_ nhotmodem-thermal . D Rtripstrip-point0 b_ nhotvph-pwr-regulator2regulator-fixed vph_pwr &8u  >8u pm8998-smps42regulator-fixed vreg_s4a_1p8 &w@ >w@ m   interrupt-parent#address-cells#size-cellsmodelcompatiblei2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9i2c10i2c11i2c12i2c13i2c14i2c15spi0spi1spi2spi3spi4spi5spi6spi7spi8spi9spi10spi11spi12spi13spi14spi15serial0stdout-pathdevice_typeregrangesno-mapphandleqcom,client-idqcom,vmidenable-methodcpu-idle-statescapacity-dmips-mhzdynamic-power-coefficientqcom,freq-domain#cooling-cellsnext-level-cachecpuentry-methodidle-state-namearm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslocal-timer-stopinterrupts#clock-cellsclock-frequencyclock-output-namesinterrupts-extendedinterrupt-namesclocksclock-namesmemory-regionqcom,smem-statesqcom,smem-state-namesstatuslabelqcom,remote-pidmboxesqcom,glink-channelsiommussyscon#hwlock-cellshwlocksqcom,smemqcom,local-pidqcom,entry-name#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsdma-ranges#reset-cells#power-domain-cellsprotected-clocksbitspinctrl-namespinctrl-0reg-namesphysphy-nameslanes-per-directionpower-domainsfreq-table-hzreset-gpiosvcc-supplyvcc-max-microampresetsreset-namesvdda-phy-supplyvdda-pll-supply#phy-cellsgpio-controller#gpio-cellsgpio-rangesgpio-reserved-rangespinsfunctiondrive-strengthbias-disablebias-pull-upqcom,halt-regspower-domain-namesremote-endpointarm,scatter-gathervmmc-supplyvqmmc-supplycd-gpiosnvmem-cellsvdd-supplyvdda-phy-dpdm-supplyqcom,imp-res-offset-valueqcom,hstx-trim-valueqcom,preemphasis-levelqcom,preemphasis-widthassigned-clocksassigned-clock-ratessnps,dis_u2_susphy_quirksnps,dis_enblslpm_quirkdr_mode#stream-id-cellsoperating-points-v2qcom,gmuopp-hzopp-level#iommu-cells#global-interrupts#qcom,sensors#thermal-sensor-cellsqcom,eeqcom,channelcell-index#mbox-cellsqcom,tcs-offsetqcom,drv-idqcom,tcs-config#interconnect-cellsqcom,pmic-idvdd-s1-supplyvdd-s2-supplyvdd-s3-supplyvdd-s4-supplyvdd-s5-supplyvdd-s6-supplyvdd-s7-supplyvdd-s8-supplyvdd-s9-supplyvdd-s10-supplyvdd-s11-supplyvdd-s12-supplyvdd-s13-supplyvdd-l1-l27-supplyvdd-l2-l8-l17-supplyvdd-l3-l11-supplyvdd-l4-l5-supplyvdd-l6-supplyvdd-l7-l12-l14-l15-supplyvdd-l9-supplyvdd-l10-l23-l25-supplyvdd-l13-l19-l21-supplyvdd-l16-l28-supplyvdd-l18-l22-supplyvdd-l20-l24-supplyvdd-l26-supplyvin-lvs-1-2-supplyregulator-min-microvoltregulator-max-microvoltregulator-initial-moderegulator-always-onvdd-bob-supplyregulator-allow-bypassmsi-controller#msi-cellsframe-number#freq-domain-cellsvdd-0.8-cx-mx-supplyvdd-1.8-xo-supplyvdd-1.3-rfa-supplyvdd-3.3-ch0-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceregulator-nameregulator-boot-onvin-supply